1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This describes the calling conventions for Mips architecture. 10 //===----------------------------------------------------------------------===// 11 12 /// CCIfSubtarget - Match if the current subtarget has a feature F. 13 class CCIfSubtarget<string F, CCAction A, string Invert = ""> 14 : CCIf<!strconcat(Invert, 15 "static_cast<const MipsSubtarget&>" 16 "(State.getMachineFunction().getSubtarget()).", 17 F), 18 A>; 19 20 // The inverse of CCIfSubtarget 21 class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">; 22 23 /// Match if the original argument (before lowering) was a float. 24 /// For example, this is true for i32's that were lowered from soft-float. 25 class CCIfOrigArgWasNotFloat<CCAction A> 26 : CCIf<"!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)", 27 A>; 28 29 /// Match if the original argument (before lowering) was a 128-bit float (i.e. 30 /// long double). 31 class CCIfOrigArgWasF128<CCAction A> 32 : CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", A>; 33 34 /// Match if this specific argument is a vararg. 35 /// This is slightly different fro CCIfIsVarArg which matches if any argument is 36 /// a vararg. 37 class CCIfArgIsVarArg<CCAction A> 38 : CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)", A>; 39 40 /// Match if the return was a floating point vector. 41 class CCIfOrigArgWasNotVectorFloat<CCAction A> 42 : CCIf<"!static_cast<MipsCCState *>(&State)" 43 "->WasOriginalRetVectorFloat(ValNo)", A>; 44 45 /// Match if the special calling conv is the specified value. 46 class CCIfSpecialCallingConv<string CC, CCAction A> 47 : CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == " 48 "MipsCCState::" # CC, A>; 49 50 // For soft-float, f128 values are returned in A0_64 rather than V1_64. 51 def RetCC_F128SoftFloat : CallingConv<[ 52 CCAssignToReg<[V0_64, A0_64]> 53 ]>; 54 55 // For hard-float, f128 values are returned as a pair of f64's rather than a 56 // pair of i64's. 57 def RetCC_F128HardFloat : CallingConv<[ 58 CCBitConvertToType<f64>, 59 60 // Contrary to the ABI documentation, a struct containing a long double is 61 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to 62 // match the de facto ABI as implemented by GCC. 63 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>, 64 65 CCAssignToReg<[D0_64, D2_64]> 66 ]>; 67 68 // Handle F128 specially since we can't identify the original type during the 69 // tablegen-erated code. 70 def RetCC_F128 : CallingConv<[ 71 CCIfSubtarget<"useSoftFloat()", 72 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>, 73 CCIfSubtargetNot<"useSoftFloat()", 74 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>> 75 ]>; 76 77 //===----------------------------------------------------------------------===// 78 // Mips O32 Calling Convention 79 //===----------------------------------------------------------------------===// 80 81 def CC_MipsO32 : CallingConv<[ 82 // Promote i8/i16 arguments to i32. 83 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 84 85 // Integer values get stored in stack slots that are 4 bytes in 86 // size and 4-byte aligned. 87 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 88 89 // Integer values get stored in stack slots that are 8 bytes in 90 // size and 8-byte aligned. 91 CCIfType<[f64], CCAssignToStack<8, 8>> 92 ]>; 93 94 // Only the return rules are defined here for O32. The rules for argument 95 // passing are defined in MipsISelLowering.cpp. 96 def RetCC_MipsO32 : CallingConv<[ 97 // Promote i1/i8/i16 return values to i32. 98 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 99 100 // i32 are returned in registers V0, V1, A0, A1, unless the original return 101 // type was a vector of floats. 102 CCIfOrigArgWasNotVectorFloat<CCIfType<[i32], 103 CCAssignToReg<[V0, V1, A0, A1]>>>, 104 105 // f32 are returned in registers F0, F2 106 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 107 108 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or 109 // in D0 and D1 in FP32bit mode. 110 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>, 111 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>> 112 ]>; 113 114 def CC_MipsO32_FP32 : CustomCallingConv; 115 def CC_MipsO32_FP64 : CustomCallingConv; 116 117 def CC_MipsO32_FP : CallingConv<[ 118 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>, 119 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>> 120 ]>; 121 122 //===----------------------------------------------------------------------===// 123 // Mips N32/64 Calling Convention 124 //===----------------------------------------------------------------------===// 125 126 def CC_MipsN_SoftFloat : CallingConv<[ 127 CCAssignToRegWithShadow<[A0, A1, A2, A3, 128 T0, T1, T2, T3], 129 [D12_64, D13_64, D14_64, D15_64, 130 D16_64, D17_64, D18_64, D19_64]>, 131 CCAssignToStack<4, 8> 132 ]>; 133 134 def CC_MipsN : CallingConv<[ 135 CCIfType<[i8, i16, i32, i64], 136 CCIfSubtargetNot<"isLittle()", 137 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 138 139 // All integers (except soft-float integers) are promoted to 64-bit. 140 CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>, 141 142 // The only i32's we have left are soft-float arguments. 143 CCIfSubtarget<"useSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>, 144 145 // Integer arguments are passed in integer registers. 146 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64, 147 T0_64, T1_64, T2_64, T3_64], 148 [D12_64, D13_64, D14_64, D15_64, 149 D16_64, D17_64, D18_64, D19_64]>>, 150 151 // f32 arguments are passed in single precision FP registers. 152 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15, 153 F16, F17, F18, F19], 154 [A0_64, A1_64, A2_64, A3_64, 155 T0_64, T1_64, T2_64, T3_64]>>, 156 157 // f64 arguments are passed in double precision FP registers. 158 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64, 159 D16_64, D17_64, D18_64, D19_64], 160 [A0_64, A1_64, A2_64, A3_64, 161 T0_64, T1_64, T2_64, T3_64]>>, 162 163 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 164 CCIfType<[f32], CCAssignToStack<4, 8>>, 165 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 166 ]>; 167 168 // N32/64 variable arguments. 169 // All arguments are passed in integer registers. 170 def CC_MipsN_VarArg : CallingConv<[ 171 CCIfType<[i8, i16, i32, i64], 172 CCIfSubtargetNot<"isLittle()", 173 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 174 175 // All integers are promoted to 64-bit. 176 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 177 178 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 179 180 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, 181 T0_64, T1_64, T2_64, T3_64]>>, 182 183 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 184 CCIfType<[f32], CCAssignToStack<4, 8>>, 185 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 186 ]>; 187 188 def RetCC_MipsN : CallingConv<[ 189 // f128 needs to be handled similarly to f32 and f64. However, f128 is not 190 // legal and is lowered to i128 which is further lowered to a pair of i64's. 191 // This presents us with a problem for the calling convention since hard-float 192 // still needs to pass them in FPU registers, and soft-float needs to use $v0, 193 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a 194 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on 195 // whether the result was originally an f128 into the tablegen-erated code. 196 // 197 // f128 should only occur for the N64 ABI where long double is 128-bit. On 198 // N32, long double is equivalent to double. 199 CCIfType<[i64], CCIfOrigArgWasF128<CCDelegateTo<RetCC_F128>>>, 200 201 // Aggregate returns are positioned at the lowest address in the slot for 202 // both little and big-endian targets. When passing in registers, this 203 // requires that big-endian targets shift the value into the upper bits. 204 CCIfSubtarget<"isLittle()", 205 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>, 206 CCIfSubtargetNot<"isLittle()", 207 CCIfType<[i8, i16, i32, i64], 208 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 209 210 // i64 are returned in registers V0_64, V1_64 211 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>, 212 213 // f32 are returned in registers F0, F2 214 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 215 216 // f64 are returned in registers D0, D2 217 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>> 218 ]>; 219 220 //===----------------------------------------------------------------------===// 221 // Mips FastCC Calling Convention 222 //===----------------------------------------------------------------------===// 223 def CC_MipsO32_FastCC : CallingConv<[ 224 // f64 arguments are passed in double-precision floating pointer registers. 225 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", 226 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, 227 D7, D8, D9]>>>, 228 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()", 229 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, 230 D4_64, D5_64, D6_64, D7_64, 231 D8_64, D9_64, D10_64, D11_64, 232 D12_64, D13_64, D14_64, D15_64, 233 D16_64, D17_64, D18_64, 234 D19_64]>>>>, 235 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()", 236 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64, 237 D8_64, D10_64, D12_64, D14_64, 238 D16_64, D18_64]>>>>, 239 240 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned. 241 CCIfType<[f64], CCAssignToStack<8, 8>> 242 ]>; 243 244 def CC_MipsN_FastCC : CallingConv<[ 245 // Integer arguments are passed in integer registers. 246 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64, 247 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 248 T8_64, V1_64]>>, 249 250 // f64 arguments are passed in double-precision floating pointer registers. 251 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64, 252 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64, 253 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64, 254 D18_64, D19_64]>>, 255 256 // Stack parameter slots for i64 and f64 are 64-bit doublewords and 257 // 8-byte aligned. 258 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 259 ]>; 260 261 def CC_Mips_FastCC : CallingConv<[ 262 // Handles byval parameters. 263 CCIfByVal<CCPassByVal<4, 4>>, 264 265 // Promote i8/i16 arguments to i32. 266 CCIfType<[i8, i16], CCPromoteToType<i32>>, 267 268 // Integer arguments are passed in integer registers. All scratch registers, 269 // except for AT, V0 and T9, are available to be used as argument registers. 270 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()", 271 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>, 272 273 // In NaCl, T6, T7 and T8 are reserved and not available as argument 274 // registers for fastcc. T6 contains the mask for sandboxing control flow 275 // (indirect jumps and calls). T7 contains the mask for sandboxing memory 276 // accesses (loads and stores). T8 contains the thread pointer. 277 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()", 278 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>, 279 280 // f32 arguments are passed in single-precision floating pointer registers. 281 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()", 282 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, 283 F14, F15, F16, F17, F18, F19]>>>, 284 285 // Don't use odd numbered single-precision registers for -mno-odd-spreg. 286 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()", 287 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>, 288 289 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned. 290 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 291 292 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>, 293 CCDelegateTo<CC_MipsN_FastCC> 294 ]>; 295 296 //===----------------------------------------------------------------------===// 297 // Mips Calling Convention Dispatch 298 //===----------------------------------------------------------------------===// 299 300 def RetCC_Mips : CallingConv<[ 301 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>, 302 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>, 303 CCDelegateTo<RetCC_MipsO32> 304 ]>; 305 306 def CC_Mips_ByVal : CallingConv<[ 307 CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>, 308 CCIfByVal<CCPassByVal<8, 8>> 309 ]>; 310 311 def CC_Mips16RetHelper : CallingConv<[ 312 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 313 314 // Integer arguments are passed in integer registers. 315 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>> 316 ]>; 317 318 def CC_Mips_FixedArg : CallingConv<[ 319 // Mips16 needs special handling on some functions. 320 CCIf<"State.getCallingConv() != CallingConv::Fast", 321 CCIfSpecialCallingConv<"Mips16RetHelperConv", 322 CCDelegateTo<CC_Mips16RetHelper>>>, 323 324 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 325 326 // f128 needs to be handled similarly to f32 and f64 on hard-float. However, 327 // f128 is not legal and is lowered to i128 which is further lowered to a pair 328 // of i64's. 329 // This presents us with a problem for the calling convention since hard-float 330 // still needs to pass them in FPU registers. We therefore resort to a 331 // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on 332 // whether the argument was originally an f128 into the tablegen-erated code. 333 // 334 // f128 should only occur for the N64 ABI where long double is 128-bit. On 335 // N32, long double is equivalent to double. 336 CCIfType<[i64], 337 CCIfSubtargetNot<"useSoftFloat()", 338 CCIfOrigArgWasF128<CCBitConvertToType<f64>>>>, 339 340 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>, 341 342 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>, 343 CCDelegateTo<CC_MipsN> 344 ]>; 345 346 def CC_Mips_VarArg : CallingConv<[ 347 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 348 349 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>, 350 CCDelegateTo<CC_MipsN_VarArg> 351 ]>; 352 353 def CC_Mips : CallingConv<[ 354 CCIfVarArg<CCIfArgIsVarArg<CCDelegateTo<CC_Mips_VarArg>>>, 355 CCDelegateTo<CC_Mips_FixedArg> 356 ]>; 357 358 //===----------------------------------------------------------------------===// 359 // Callee-saved register lists. 360 //===----------------------------------------------------------------------===// 361 362 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP, 363 (sequence "S%u", 7, 0))>; 364 365 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 366 (sequence "S%u", 7, 0))> { 367 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2)); 368 } 369 370 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 371 (sequence "S%u", 7, 0))>; 372 373 def CSR_O32_FP64 : 374 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP, 375 (sequence "S%u", 7, 0))>; 376 377 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64, 378 D30_64, RA_64, FP_64, GP_64, 379 (sequence "S%u_64", 7, 0))>; 380 381 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64, 382 GP_64, (sequence "S%u_64", 7, 0))>; 383 384 def CSR_Mips16RetHelper : 385 CalleeSavedRegs<(add V0, V1, FP, 386 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0), 387 (sequence "D%u", 15, 10))>; 388 389 def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0), 390 (sequence "S%u", 7, 0), 391 (sequence "V%u", 1, 0), 392 (sequence "T%u", 9, 0), 393 RA, FP, GP, AT)>; 394 395 def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0), 396 (sequence "S%u", 7, 0), 397 (sequence "V%u", 1, 0), 398 (sequence "T%u", 9, 0), 399 RA, FP, GP, AT, LO0, HI0)>; 400 401 def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0), 402 (sequence "V%u_64", 1, 0), 403 (sequence "S%u_64", 7, 0), 404 (sequence "T%u_64", 9, 0), 405 RA_64, FP_64, GP_64, AT_64)>; 406 407 def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0), 408 (sequence "S%u_64", 7, 0), 409 (sequence "T%u_64", 9, 0), 410 (sequence "V%u_64", 1, 0), 411 RA_64, FP_64, GP_64, AT_64, 412 LO0_64, HI0_64)>; 413
