1 //===- MipsEVAInstrInfo.td - EVA ASE instructions -*- tablegen ------------*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips EVA ASE instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // 16 // Instruction encodings 17 // 18 //===----------------------------------------------------------------------===// 19 20 // Memory Load/Store EVA encodings 21 class LBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LBE>; 22 class LBuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LBuE>; 23 class LHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LHE>; 24 class LHuE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LHuE>; 25 class LWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWE>; 26 27 class SBE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SBE>; 28 class SHE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SHE>; 29 class SWE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWE>; 30 31 // load/store left/right EVA encodings 32 class LWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWLE>; 33 class LWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LWRE>; 34 class SWLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWLE>; 35 class SWRE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SWRE>; 36 37 // Load-linked EVA, Store-conditional EVA encodings 38 class LLE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_LLE>; 39 class SCE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_SCE>; 40 41 class TLBINV_ENC : TLB_FM<OPCODE6_TLBINV>; 42 class TLBINVF_ENC : TLB_FM<OPCODE6_TLBINVF>; 43 44 class CACHEE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_CACHEE>; 45 class PREFE_ENC : SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6_PREFE>; 46 47 //===----------------------------------------------------------------------===// 48 // 49 // Instruction descriptions 50 // 51 //===----------------------------------------------------------------------===// 52 53 // Memory Load/Store EVA descriptions 54 class LOAD_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 55 InstrItinClass itin = NoItinerary> { 56 dag OutOperandList = (outs GPROpnd:$rt); 57 dag InOperandList = (ins mem_simm9:$addr); 58 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 59 list<dag> Pattern = []; 60 string DecoderMethod = "DecodeMemEVA"; 61 bit canFoldAsLoad = 1; 62 string BaseOpcode = instr_asm; 63 bit mayLoad = 1; 64 InstrItinClass Itinerary = itin; 65 } 66 67 class LBE_DESC : LOAD_EVA_DESC_BASE<"lbe", GPR32Opnd, II_LBE>; 68 class LBuE_DESC : LOAD_EVA_DESC_BASE<"lbue", GPR32Opnd, II_LBUE>; 69 class LHE_DESC : LOAD_EVA_DESC_BASE<"lhe", GPR32Opnd, II_LHE>; 70 class LHuE_DESC : LOAD_EVA_DESC_BASE<"lhue", GPR32Opnd, II_LHUE>; 71 class LWE_DESC : LOAD_EVA_DESC_BASE<"lwe", GPR32Opnd, II_LWE>; 72 73 class STORE_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 74 SDPatternOperator OpNode = null_frag, 75 InstrItinClass itin = NoItinerary> { 76 dag OutOperandList = (outs); 77 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 78 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 79 list<dag> Pattern = []; 80 string DecoderMethod = "DecodeMemEVA"; 81 string BaseOpcode = instr_asm; 82 bit mayStore = 1; 83 InstrItinClass Itinerary = itin; 84 } 85 86 class SBE_DESC : STORE_EVA_DESC_BASE<"sbe", GPR32Opnd, null_frag, II_SBE>; 87 class SHE_DESC : STORE_EVA_DESC_BASE<"she", GPR32Opnd, null_frag, II_SHE>; 88 class SWE_DESC : STORE_EVA_DESC_BASE<"swe", GPR32Opnd, null_frag, II_SWE>; 89 90 // Load/Store Left/Right EVA descriptions 91 class LOAD_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 92 InstrItinClass itin = NoItinerary> { 93 dag OutOperandList = (outs GPROpnd:$rt); 94 dag InOperandList = (ins mem_simm9:$addr, GPROpnd:$src); 95 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 96 list<dag> Pattern = []; 97 string DecoderMethod = "DecodeMemEVA"; 98 string BaseOpcode = instr_asm; 99 string Constraints = "$src = $rt"; 100 bit canFoldAsLoad = 1; 101 InstrItinClass Itinerary = itin; 102 bit mayLoad = 1; 103 bit mayStore = 0; 104 } 105 106 class LWLE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwle", GPR32Opnd, II_LWLE>; 107 class LWRE_DESC : LOAD_LEFT_RIGHT_EVA_DESC_BASE<"lwre", GPR32Opnd, II_LWRE>; 108 109 class STORE_LEFT_RIGHT_EVA_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 110 InstrItinClass itin = NoItinerary> { 111 dag OutOperandList = (outs); 112 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 113 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 114 list<dag> Pattern = []; 115 string DecoderMethod = "DecodeMemEVA"; 116 string BaseOpcode = instr_asm; 117 InstrItinClass Itinerary = itin; 118 bit mayLoad = 0; 119 bit mayStore = 1; 120 } 121 122 class SWLE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swle", GPR32Opnd, II_SWLE>; 123 class SWRE_DESC : STORE_LEFT_RIGHT_EVA_DESC_BASE<"swre", GPR32Opnd, II_SWRE>; 124 125 // Load-linked EVA, Store-conditional EVA descriptions 126 class LLE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 127 InstrItinClass itin = NoItinerary> { 128 dag OutOperandList = (outs GPROpnd:$rt); 129 dag InOperandList = (ins mem_simm9:$addr); 130 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 131 list<dag> Pattern = []; 132 string BaseOpcode = instr_asm; 133 bit mayLoad = 1; 134 string DecoderMethod = "DecodeMemEVA"; 135 InstrItinClass Itinerary = itin; 136 } 137 138 class LLE_DESC : LLE_DESC_BASE<"lle", GPR32Opnd, II_LLE>; 139 140 class SCE_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, 141 InstrItinClass itin = NoItinerary> { 142 dag OutOperandList = (outs GPROpnd:$dst); 143 dag InOperandList = (ins GPROpnd:$rt, mem_simm9:$addr); 144 string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); 145 list<dag> Pattern = []; 146 string BaseOpcode = instr_asm; 147 bit mayStore = 1; 148 string Constraints = "$rt = $dst"; 149 string DecoderMethod = "DecodeMemEVA"; 150 InstrItinClass Itinerary = itin; 151 } 152 153 class SCE_DESC : SCE_DESC_BASE<"sce", GPR32Opnd, II_SCE>; 154 155 class TLB_DESC_BASE<string instr_asm, InstrItinClass itin = NoItinerary> { 156 dag OutOperandList = (outs); 157 dag InOperandList = (ins); 158 string AsmString = instr_asm; 159 list<dag> Pattern = []; 160 InstrItinClass Itinerary = itin; 161 } 162 163 class TLBINV_DESC : TLB_DESC_BASE<"tlbinv", II_TLBINV>; 164 class TLBINVF_DESC : TLB_DESC_BASE<"tlbinvf", II_TLBINVF>; 165 166 class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd, 167 InstrItinClass itin = NoItinerary> { 168 dag OutOperandList = (outs); 169 dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); 170 string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); 171 list<dag> Pattern = []; 172 string BaseOpcode = instr_asm; 173 string DecoderMethod = "DecodeCacheeOp_CacheOpR6"; 174 InstrItinClass Itinerary = itin; 175 } 176 177 class CACHEE_DESC : CACHEE_DESC_BASE<"cachee", mem_simm9, II_CACHEE>; 178 class PREFE_DESC : CACHEE_DESC_BASE<"prefe", mem_simm9, II_PREFE>; 179 180 //===----------------------------------------------------------------------===// 181 // 182 // Instruction definitions 183 // 184 //===----------------------------------------------------------------------===// 185 186 let AdditionalPredicates = [NotInMicroMips] in { 187 /// Load and Store EVA Instructions 188 def LBE : MMRel, LBE_ENC, LBE_DESC, ISA_MIPS32R2, ASE_EVA; 189 def LBuE : MMRel, LBuE_ENC, LBuE_DESC, ISA_MIPS32R2, ASE_EVA; 190 def LHE : MMRel, LHE_ENC, LHE_DESC, ISA_MIPS32R2, ASE_EVA; 191 def LHuE : MMRel, LHuE_ENC, LHuE_DESC, ISA_MIPS32R2, ASE_EVA; 192 def LWE : MMRel, LWE_ENC, LWE_DESC, ISA_MIPS32R2, ASE_EVA; 193 def SBE : MMRel, SBE_ENC, SBE_DESC, ISA_MIPS32R2, ASE_EVA; 194 def SHE : MMRel, SHE_ENC, SHE_DESC, ISA_MIPS32R2, ASE_EVA; 195 def SWE : MMRel, SWE_ENC, SWE_DESC, ISA_MIPS32R2, ASE_EVA; 196 197 /// load/store left/right EVA 198 def LWLE : MMRel, LWLE_ENC, LWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 199 def LWRE : MMRel, LWRE_ENC, LWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 200 def SWLE : MMRel, SWLE_ENC, SWLE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 201 def SWRE : MMRel, SWRE_ENC, SWRE_DESC, ISA_MIPS32R2_NOT_32R6_64R6, ASE_EVA; 202 203 /// Load-linked EVA, Store-conditional EVA 204 def LLE : MMRel, LLE_ENC, LLE_DESC, ISA_MIPS32R2, ASE_EVA; 205 def SCE : MMRel, SCE_ENC, SCE_DESC, ISA_MIPS32R2, ASE_EVA; 206 207 /// TLB invalidate instructions 208 def TLBINV : TLBINV_ENC, TLBINV_DESC, ISA_MIPS32R2, ASE_EVA; 209 def TLBINVF : TLBINVF_ENC, TLBINVF_DESC, ISA_MIPS32R2, ASE_EVA; 210 211 /// EVA versions of cache and pref 212 def CACHEE : MMRel, CACHEE_ENC, CACHEE_DESC, ISA_MIPS32R2, ASE_EVA; 213 def PREFE : MMRel, PREFE_ENC, PREFE_DESC, ISA_MIPS32R2, ASE_EVA; 214 } 215
