1 //===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Mips FPU instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Floating Point Instructions 16 // ------------------------ 17 // * 64bit fp: 18 // - 32 64-bit registers (default mode) 19 // - 16 even 32-bit registers (32-bit compatible mode) for 20 // single and double access. 21 // * 32bit fp: 22 // - 16 even 32-bit registers - single and double (aliased) 23 // - 32 32-bit registers (within single-only mode) 24 //===----------------------------------------------------------------------===// 25 26 // Floating Point Compare and Branch 27 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, 28 SDTCisVT<1, i32>, 29 SDTCisVT<2, OtherVT>]>; 30 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 31 SDTCisVT<2, i32>]>; 32 def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, 33 SDTCisSameAs<1, 3>]>; 34 def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; 35 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 36 SDTCisVT<1, i32>, 37 SDTCisSameAs<1, 2>]>; 38 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 39 SDTCisVT<1, f64>, 40 SDTCisVT<2, i32>]>; 41 42 def SDT_MipsMTC1_D64 : SDTypeProfile<1, 1, [SDTCisVT<0, f64>, 43 SDTCisVT<1, i32>]>; 44 45 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 46 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 47 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 48 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 49 [SDNPHasChain, SDNPOptInGlue]>; 50 def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; 51 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 52 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 53 SDT_MipsExtractElementF64>; 54 55 def MipsMTC1_D64 : SDNode<"MipsISD::MTC1_D64", SDT_MipsMTC1_D64>; 56 57 // Operand for printing out a condition code. 58 let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in 59 def condcode : Operand<i32>; 60 61 //===----------------------------------------------------------------------===// 62 // Feature predicates. 63 //===----------------------------------------------------------------------===// 64 65 def IsFP64bit : Predicate<"Subtarget->isFP64bit()">, 66 AssemblerPredicate<"FeatureFP64Bit">; 67 def NotFP64bit : Predicate<"!Subtarget->isFP64bit()">, 68 AssemblerPredicate<"!FeatureFP64Bit">; 69 def IsSingleFloat : Predicate<"Subtarget->isSingleFloat()">, 70 AssemblerPredicate<"FeatureSingleFloat">; 71 def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">, 72 AssemblerPredicate<"!FeatureSingleFloat">; 73 def IsNotSoftFloat : Predicate<"!Subtarget->useSoftFloat()">, 74 AssemblerPredicate<"!FeatureSoftFloat">; 75 76 //===----------------------------------------------------------------------===// 77 // Mips FGR size adjectives. 78 // They are mutually exclusive. 79 //===----------------------------------------------------------------------===// 80 81 class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; } 82 class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; } 83 class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; } 84 85 //===----------------------------------------------------------------------===// 86 87 // FP immediate patterns. 88 def fpimm0 : PatLeaf<(fpimm), [{ 89 return N->isExactlyValue(+0.0); 90 }]>; 91 92 def fpimm0neg : PatLeaf<(fpimm), [{ 93 return N->isExactlyValue(-0.0); 94 }]>; 95 96 //===----------------------------------------------------------------------===// 97 // Instruction Class Templates 98 // 99 // A set of multiclasses is used to address the register usage. 100 // 101 // S32 - single precision in 16 32bit even fp registers 102 // single precision in 32 32bit fp registers in SingleOnly mode 103 // S64 - single precision in 32 64bit fp registers (In64BitMode) 104 // D32 - double precision in 16 32bit even fp registers 105 // D64 - double precision in 32 64bit fp registers (In64BitMode) 106 // 107 // Only S32 and D32 are supported right now. 108 //===----------------------------------------------------------------------===// 109 class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm, 110 SDPatternOperator OpNode= null_frag> : 111 InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft), 112 !strconcat(opstr, "\t$fd, $fs, $ft"), 113 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>, 114 HARDFLOAT { 115 let isCommutable = IsComm; 116 } 117 118 multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm, 119 SDPatternOperator OpNode = null_frag> { 120 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32; 121 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 { 122 string DecoderNamespace = "MipsFP64"; 123 } 124 } 125 126 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 127 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 128 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"), 129 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, 130 HARDFLOAT, 131 NeverHasSideEffects; 132 133 multiclass ABSS_M<string opstr, InstrItinClass Itin, 134 SDPatternOperator OpNode= null_frag> { 135 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>, 136 FGR_32; 137 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 { 138 string DecoderNamespace = "MipsFP64"; 139 } 140 } 141 142 multiclass ROUND_M<string opstr, InstrItinClass Itin> { 143 def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32; 144 def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 { 145 let DecoderNamespace = "MipsFP64"; 146 } 147 } 148 149 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 150 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 151 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"), 152 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT { 153 let isMoveReg = 1; 154 } 155 156 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 157 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> : 158 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"), 159 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT { 160 let isMoveReg = 1; 161 } 162 163 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, 164 InstrItinClass Itin> : 165 InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt), 166 !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT { 167 // $fs_in is part of a white lie to work around a widespread bug in the FPU 168 // implementation. See expandBuildPairF64 for details. 169 let Constraints = "$fs = $fs_in"; 170 } 171 172 class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO, 173 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 174 InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 175 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>, 176 HARDFLOAT { 177 let DecoderMethod = "DecodeFMem"; 178 let mayLoad = 1; 179 } 180 181 class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO, 182 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 183 InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), 184 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT { 185 let DecoderMethod = "DecodeFMem"; 186 let mayStore = 1; 187 } 188 189 class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 190 SDPatternOperator OpNode = null_frag> : 191 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 192 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 193 [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, 194 FrmFR, opstr>, HARDFLOAT; 195 196 class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, 197 SDPatternOperator OpNode = null_frag> : 198 InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft), 199 !strconcat(opstr, "\t$fd, $fr, $fs, $ft"), 200 [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))], 201 Itin, FrmFR, opstr>, HARDFLOAT; 202 203 class LWXC1_FT<string opstr, RegisterOperand DRC, 204 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 205 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index), 206 !strconcat(opstr, "\t$fd, ${index}(${base})"), 207 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin, 208 FrmFI, opstr>, HARDFLOAT { 209 let AddedComplexity = 20; 210 } 211 212 class SWXC1_FT<string opstr, RegisterOperand DRC, 213 InstrItinClass Itin, SDPatternOperator OpNode = null_frag> : 214 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index), 215 !strconcat(opstr, "\t$fs, ${index}(${base})"), 216 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin, 217 FrmFI, opstr>, HARDFLOAT { 218 let AddedComplexity = 20; 219 } 220 221 class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, 222 SDPatternOperator Op = null_frag> : 223 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 224 !strconcat(opstr, "\t$fcc, $offset"), 225 [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, 226 FrmFI, opstr>, HARDFLOAT { 227 let isBranch = 1; 228 let isTerminator = 1; 229 let hasDelaySlot = 1; 230 let Defs = [AT]; 231 let hasFCCRegOperand = 1; 232 } 233 234 class BC1XL_FT<string opstr, DAGOperand opnd, InstrItinClass Itin> : 235 InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), 236 !strconcat(opstr, "\t$fcc, $offset"), [], Itin, 237 FrmFI, opstr>, HARDFLOAT { 238 let isBranch = 1; 239 let isTerminator = 1; 240 let hasDelaySlot = 1; 241 let Defs = [AT]; 242 let hasFCCRegOperand = 1; 243 } 244 245 class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, 246 SDPatternOperator OpNode = null_frag> : 247 InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), 248 !strconcat("c.$cond.", typestr, "\t$fs, $ft"), 249 [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR, 250 !strconcat("c.$cond.", typestr)>, HARDFLOAT { 251 let Defs = [FCC0]; 252 let isCodeGenOnly = 1; 253 let hasFCCRegOperand = 1; 254 } 255 256 257 // Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather 258 // duplicating the instruction definition for MIPS1 - MIPS3, we expand 259 // c.cond.ft if necessary, and reject it after constructing the 260 // instruction if the ISA doesn't support it. 261 class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, 262 InstrItinClass itin> : 263 InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft), 264 !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin, 265 FrmFR>, HARDFLOAT { 266 let isCompare = 1; 267 let hasFCCRegOperand = 1; 268 } 269 270 271 multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, 272 InstrItinClass itin> { 273 def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, 274 C_COND_FM<fmt, 0> { 275 let BaseOpcode = "c.f."#NAME; 276 let isCommutable = 1; 277 } 278 def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, 279 C_COND_FM<fmt, 1> { 280 let BaseOpcode = "c.un."#NAME; 281 let isCommutable = 1; 282 } 283 def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, 284 C_COND_FM<fmt, 2> { 285 let BaseOpcode = "c.eq."#NAME; 286 let isCommutable = 1; 287 } 288 def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, 289 C_COND_FM<fmt, 3> { 290 let BaseOpcode = "c.ueq."#NAME; 291 let isCommutable = 1; 292 } 293 def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, 294 C_COND_FM<fmt, 4> { 295 let BaseOpcode = "c.olt."#NAME; 296 } 297 def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, 298 C_COND_FM<fmt, 5> { 299 let BaseOpcode = "c.ult."#NAME; 300 } 301 def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, 302 C_COND_FM<fmt, 6> { 303 let BaseOpcode = "c.ole."#NAME; 304 } 305 def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, 306 C_COND_FM<fmt, 7> { 307 let BaseOpcode = "c.ule."#NAME; 308 } 309 def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, 310 C_COND_FM<fmt, 8> { 311 let BaseOpcode = "c.sf."#NAME; 312 let isCommutable = 1; 313 } 314 def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, 315 C_COND_FM<fmt, 9> { 316 let BaseOpcode = "c.ngle."#NAME; 317 } 318 def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, 319 C_COND_FM<fmt, 10> { 320 let BaseOpcode = "c.seq."#NAME; 321 let isCommutable = 1; 322 } 323 def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, 324 C_COND_FM<fmt, 11> { 325 let BaseOpcode = "c.ngl."#NAME; 326 } 327 def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, 328 C_COND_FM<fmt, 12> { 329 let BaseOpcode = "c.lt."#NAME; 330 } 331 def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, 332 C_COND_FM<fmt, 13> { 333 let BaseOpcode = "c.nge."#NAME; 334 } 335 def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, 336 C_COND_FM<fmt, 14> { 337 let BaseOpcode = "c.le."#NAME; 338 } 339 def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, 340 C_COND_FM<fmt, 15> { 341 let BaseOpcode = "c.ngt."#NAME; 342 } 343 } 344 345 let AdditionalPredicates = [NotInMicroMips] in { 346 defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; 347 defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 348 FGR_32; 349 let DecoderNamespace = "MipsFP64" in 350 defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, 351 FGR_64; 352 } 353 //===----------------------------------------------------------------------===// 354 // Floating Point Instructions 355 //===----------------------------------------------------------------------===// 356 let AdditionalPredicates = [NotInMicroMips] in { 357 def ROUND_W_S : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, 358 ABSS_FM<0xc, 16>, ISA_MIPS2; 359 defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2; 360 def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, 361 ABSS_FM<0xd, 16>, ISA_MIPS2; 362 def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, 363 ABSS_FM<0xe, 16>, ISA_MIPS2; 364 def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, 365 ABSS_FM<0xf, 16>, ISA_MIPS2; 366 def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, 367 ABSS_FM<0x24, 16>, ISA_MIPS1; 368 369 defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2; 370 defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; 371 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; 372 defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>, ISA_MIPS1; 373 } 374 375 let AdditionalPredicates = [NotInMicroMips] in { 376 def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, 377 ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2; 378 def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>, 379 ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 { 380 let BaseOpcode = "RECIP_D32"; 381 } 382 let DecoderNamespace = "MipsFP64" in 383 def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, 384 II_RECIP_D>, ABSS_FM<0b010101, 0x11>, 385 INSN_MIPS4_32R2, FGR_64; 386 def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>, 387 ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2; 388 def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>, 389 ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 { 390 let BaseOpcode = "RSQRT_D32"; 391 } 392 let DecoderNamespace = "MipsFP64" in 393 def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, 394 II_RSQRT_D>, ABSS_FM<0b010110, 0x11>, 395 INSN_MIPS4_32R2, FGR_64; 396 } 397 let DecoderNamespace = "MipsFP64" in { 398 let AdditionalPredicates = [NotInMicroMips] in { 399 def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, 400 ABSS_FM<0x8, 16>, ISA_MIPS2, FGR_64; 401 def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, 402 ABSS_FM<0x8, 17>, INSN_MIPS3_32, FGR_64; 403 def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, 404 ABSS_FM<0x9, 16>, ISA_MIPS2, FGR_64; 405 def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, 406 ABSS_FM<0x9, 17>, INSN_MIPS3_32, FGR_64; 407 def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>, 408 ABSS_FM<0xa, 16>, ISA_MIPS2, FGR_64; 409 def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>, 410 ABSS_FM<0xa, 17>, INSN_MIPS3_32, FGR_64; 411 def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>, 412 ABSS_FM<0xb, 16>, ISA_MIPS2, FGR_64; 413 def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, 414 ABSS_FM<0xb, 17>, INSN_MIPS3_32, FGR_64; 415 } 416 } 417 418 let AdditionalPredicates = [NotInMicroMips] in{ 419 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, 420 ABSS_FM<0x20, 20>, ISA_MIPS1; 421 def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>, 422 ABSS_FM<0x25, 16>, INSN_MIPS3_32R2; 423 def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, 424 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2; 425 } 426 427 let AdditionalPredicates = [NotInMicroMips] in { 428 def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, 429 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_32; 430 def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>, 431 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_32; 432 def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, 433 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_32; 434 } 435 let DecoderNamespace = "MipsFP64" in { 436 let AdditionalPredicates = [NotInMicroMips] in { 437 def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, 438 ABSS_FM<0x20, 21>, INSN_MIPS3_32R2, FGR_64; 439 def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, 440 ABSS_FM<0x20, 17>, ISA_MIPS1, FGR_64; 441 def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>, 442 ABSS_FM<0x21, 20>, ISA_MIPS1, FGR_64; 443 def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>, 444 ABSS_FM<0x21, 16>, ISA_MIPS1, FGR_64; 445 def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>, 446 ABSS_FM<0x21, 21>, INSN_MIPS3_32R2, FGR_64; 447 } 448 } 449 450 let isPseudo = 1, isCodeGenOnly = 1 in { 451 def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>; 452 def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>; 453 def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 454 def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>; 455 def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>; 456 } 457 458 let AdditionalPredicates = [NotInMicroMips] in { 459 def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>, 460 ABSS_FM<0x5, 16>, ISA_MIPS1; 461 defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>, ISA_MIPS1; 462 } 463 464 def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>, 465 ABSS_FM<0x7, 16>, ISA_MIPS1; 466 let AdditionalPredicates = [NotInMicroMips] in { 467 defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>, ISA_MIPS1; 468 } 469 470 let AdditionalPredicates = [NotInMicroMips] in { 471 def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, 472 II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; 473 defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; 474 } 475 476 // The odd-numbered registers are only referenced when doing loads, 477 // stores, and moves between floating-point and integer registers. 478 // When defining instructions, we reference all 32-bit registers, 479 // regardless of register aliasing. 480 481 /// Move Control Registers From/To CPU Registers 482 let AdditionalPredicates = [NotInMicroMips] in { 483 def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>, 484 ISA_MIPS1; 485 def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>, 486 ISA_MIPS1; 487 488 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, 489 bitconvert>, MFC1_FM<0>, ISA_MIPS1; 490 def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>, 491 ISA_MIPS1, FGR_64 { 492 let DecoderNamespace = "MipsFP64"; 493 } 494 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, 495 bitconvert>, MFC1_FM<4>, ISA_MIPS1; 496 def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>, 497 ISA_MIPS1, FGR_64 { 498 let DecoderNamespace = "MipsFP64"; 499 } 500 501 def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, 502 MFC1_FM<3>, ISA_MIPS32R2, FGR_32; 503 def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, 504 MFC1_FM<3>, ISA_MIPS32R2, FGR_64 { 505 let DecoderNamespace = "MipsFP64"; 506 } 507 508 def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, 509 MFC1_FM<7>, ISA_MIPS32R2, FGR_32; 510 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, 511 MFC1_FM<7>, ISA_MIPS32R2, FGR_64 { 512 let DecoderNamespace = "MipsFP64"; 513 } 514 515 def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, 516 bitconvert>, MFC1_FM<5>, ISA_MIPS3; 517 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, 518 bitconvert>, MFC1_FM<1>, ISA_MIPS3; 519 let isMoveReg = 1 in { 520 def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, 521 ABSS_FM<0x6, 16>, ISA_MIPS1; 522 def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, 523 ABSS_FM<0x6, 17>, ISA_MIPS1, FGR_32; 524 def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, 525 ABSS_FM<0x6, 17>, ISA_MIPS1, FGR_64 { 526 let DecoderNamespace = "MipsFP64"; 527 } 528 } // isMoveReg 529 } 530 531 /// Floating Point Memory Instructions 532 let AdditionalPredicates = [NotInMicroMips] in { 533 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>, 534 LW_FM<0x31>, ISA_MIPS1; 535 def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>, 536 LW_FM<0x39>, ISA_MIPS1; 537 } 538 539 let DecoderNamespace = "MipsFP64", AdditionalPredicates = [NotInMicroMips] in { 540 def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>, 541 LW_FM<0x35>, ISA_MIPS2, FGR_64 { 542 let BaseOpcode = "LDC164"; 543 } 544 def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>, 545 LW_FM<0x3d>, ISA_MIPS2, FGR_64; 546 } 547 548 let AdditionalPredicates = [NotInMicroMips] in { 549 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1, 550 load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 { 551 let BaseOpcode = "LDC132"; 552 } 553 def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>, 554 LW_FM<0x3d>, ISA_MIPS2, FGR_32; 555 } 556 557 // Indexed loads and stores. 558 // Base register + offset register addressing mode (indicated by "x" in the 559 // instruction mnemonic) is disallowed under NaCl. 560 let AdditionalPredicates = [IsNotNaCl] in { 561 def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>, 562 INSN_MIPS4_32R2_NOT_32R6_64R6; 563 def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>, 564 INSN_MIPS4_32R2_NOT_32R6_64R6; 565 } 566 567 let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in { 568 def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 569 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 570 def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 571 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 572 } 573 574 let DecoderNamespace="MipsFP64" in { 575 def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>, 576 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 577 def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>, 578 INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 579 } 580 581 // Load/store doubleword indexed unaligned. 582 // FIXME: This instruction should not be defined for FGR_32. 583 let AdditionalPredicates = [IsNotNaCl, NotInMicroMips] in { 584 def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 585 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 586 def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 587 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32; 588 } 589 590 let AdditionalPredicates = [IsNotNaCl, NotInMicroMips], 591 DecoderNamespace="MipsFP64" in { 592 def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, 593 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 594 def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, 595 INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64; 596 } 597 598 /// Floating-point Aritmetic 599 let AdditionalPredicates = [NotInMicroMips] in { 600 def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>, 601 ADDS_FM<0x00, 16>, ISA_MIPS1; 602 defm FADD : ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>, 603 ISA_MIPS1; 604 def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>, 605 ADDS_FM<0x03, 16>, ISA_MIPS1; 606 defm FDIV : ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>, 607 ISA_MIPS1; 608 def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, 609 ADDS_FM<0x02, 16>, ISA_MIPS1; 610 defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>, 611 ISA_MIPS1; 612 def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, 613 ADDS_FM<0x01, 16>, ISA_MIPS1; 614 defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>, 615 ISA_MIPS1; 616 } 617 618 let AdditionalPredicates = [NotInMicroMips, HasMadd4] in { 619 def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, 620 MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 621 def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, 622 MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 623 624 def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, 625 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 626 def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, 627 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 628 629 let DecoderNamespace = "MipsFP64" in { 630 def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, 631 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 632 def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, 633 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 634 } 635 } 636 637 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { 638 def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, 639 MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 640 def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, 641 MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; 642 643 def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, 644 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 645 def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, 646 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; 647 648 let DecoderNamespace = "MipsFP64" in { 649 def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, 650 MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 651 def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, 652 MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; 653 } 654 } 655 //===----------------------------------------------------------------------===// 656 // Floating Point Branch Codes 657 //===----------------------------------------------------------------------===// 658 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 659 // They must be kept in synch. 660 def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 661 def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 662 663 let AdditionalPredicates = [NotInMicroMips] in { 664 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>, 665 BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; 666 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>, 667 BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6; 668 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>, 669 BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; 670 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>, 671 BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; 672 673 /// Floating Point Compare 674 def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, 675 ISA_MIPS1_NOT_32R6_64R6 { 676 677 // FIXME: This is a required to work around the fact that these instructions 678 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 679 // fcc register set is used directly. 680 bits<3> fcc = 0; 681 } 682 def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 683 ISA_MIPS1_NOT_32R6_64R6, FGR_32 { 684 // FIXME: This is a required to work around the fact that these instructions 685 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 686 // fcc register set is used directly. 687 bits<3> fcc = 0; 688 } 689 } 690 let DecoderNamespace = "MipsFP64" in 691 def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, 692 ISA_MIPS1_NOT_32R6_64R6, FGR_64 { 693 // FIXME: This is a required to work around the fact that thiese instructions 694 // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the 695 // fcc register set is used directly. 696 bits<3> fcc = 0; 697 } 698 699 //===----------------------------------------------------------------------===// 700 // Floating Point Pseudo-Instructions 701 //===----------------------------------------------------------------------===// 702 703 // This pseudo instr gets expanded into 2 mtc1 instrs after register 704 // allocation. 705 class BuildPairF64Base<RegisterOperand RO> : 706 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi), 707 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))], 708 II_MTC1>; 709 710 def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; 711 def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; 712 713 // This pseudo instr gets expanded into 2 mfc1 instrs after register 714 // allocation. 715 // if n is 0, lower part of src is extracted. 716 // if n is 1, higher part of src is extracted. 717 // This node has associated scheduling information as the pre RA scheduler 718 // asserts otherwise. 719 class ExtractElementF64Base<RegisterOperand RO> : 720 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n), 721 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))], 722 II_MFC1>; 723 724 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT; 725 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT; 726 727 def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 728 (ins FGR32Opnd:$fs, GPR32Opnd:$rs), 729 "trunc.w.s\t$fd, $fs, $rs">; 730 731 def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 732 (ins AFGR64Opnd:$fs, GPR32Opnd:$rs), 733 "trunc.w.d\t$fd, $fs, $rs">, 734 FGR_32, HARDFLOAT; 735 736 def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), 737 (ins FGR64Opnd:$fs, GPR32Opnd:$rs), 738 "trunc.w.d\t$fd, $fs, $rs">, 739 FGR_64, HARDFLOAT; 740 741 def LoadImmSingleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 742 (ins imm64:$fpimm), 743 "li.s\t$rd, $fpimm">; 744 745 def LoadImmSingleFGR : MipsAsmPseudoInst<(outs StrictlyFGR32Opnd:$rd), 746 (ins imm64:$fpimm), 747 "li.s\t$rd, $fpimm">, 748 HARDFLOAT; 749 750 def LoadImmDoubleGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), 751 (ins imm64:$fpimm), 752 "li.d\t$rd, $fpimm">; 753 754 def LoadImmDoubleFGR_32 : MipsAsmPseudoInst<(outs StrictlyAFGR64Opnd:$rd), 755 (ins imm64:$fpimm), 756 "li.d\t$rd, $fpimm">, 757 FGR_32, HARDFLOAT; 758 759 def LoadImmDoubleFGR : MipsAsmPseudoInst<(outs StrictlyFGR64Opnd:$rd), 760 (ins imm64:$fpimm), 761 "li.d\t$rd, $fpimm">, 762 FGR_64, HARDFLOAT; 763 764 //===----------------------------------------------------------------------===// 765 // InstAliases. 766 //===----------------------------------------------------------------------===// 767 def : MipsInstAlias 768 <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 769 ISA_MIPS2, HARDFLOAT; 770 def : MipsInstAlias 771 <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 772 FGR_32, ISA_MIPS2, HARDFLOAT; 773 def : MipsInstAlias 774 <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 775 FGR_64, ISA_MIPS2, HARDFLOAT; 776 777 def : MipsInstAlias 778 <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, 779 ISA_MIPS2, HARDFLOAT; 780 def : MipsInstAlias 781 <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, 782 FGR_32, ISA_MIPS2, HARDFLOAT; 783 def : MipsInstAlias 784 <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, 785 FGR_64, ISA_MIPS2, HARDFLOAT; 786 787 multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> { 788 def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"), 789 (!cast<Instruction>("C_F_"#NAME) FCC0, 790 RC:$fs, RC:$ft), 1>; 791 def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"), 792 (!cast<Instruction>("C_UN_"#NAME) FCC0, 793 RC:$fs, RC:$ft), 1>; 794 def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"), 795 (!cast<Instruction>("C_EQ_"#NAME) FCC0, 796 RC:$fs, RC:$ft), 1>; 797 def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"), 798 (!cast<Instruction>("C_UEQ_"#NAME) FCC0, 799 RC:$fs, RC:$ft), 1>; 800 def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"), 801 (!cast<Instruction>("C_OLT_"#NAME) FCC0, 802 RC:$fs, RC:$ft), 1>; 803 def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"), 804 (!cast<Instruction>("C_ULT_"#NAME) FCC0, 805 RC:$fs, RC:$ft), 1>; 806 def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"), 807 (!cast<Instruction>("C_OLE_"#NAME) FCC0, 808 RC:$fs, RC:$ft), 1>; 809 def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"), 810 (!cast<Instruction>("C_ULE_"#NAME) FCC0, 811 RC:$fs, RC:$ft), 1>; 812 def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"), 813 (!cast<Instruction>("C_SF_"#NAME) FCC0, 814 RC:$fs, RC:$ft), 1>; 815 def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"), 816 (!cast<Instruction>("C_NGLE_"#NAME) FCC0, 817 RC:$fs, RC:$ft), 1>; 818 def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"), 819 (!cast<Instruction>("C_SEQ_"#NAME) FCC0, 820 RC:$fs, RC:$ft), 1>; 821 def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"), 822 (!cast<Instruction>("C_NGL_"#NAME) FCC0, 823 RC:$fs, RC:$ft), 1>; 824 def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"), 825 (!cast<Instruction>("C_LT_"#NAME) FCC0, 826 RC:$fs, RC:$ft), 1>; 827 def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"), 828 (!cast<Instruction>("C_NGE_"#NAME) FCC0, 829 RC:$fs, RC:$ft), 1>; 830 def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"), 831 (!cast<Instruction>("C_LE_"#NAME) FCC0, 832 RC:$fs, RC:$ft), 1>; 833 def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"), 834 (!cast<Instruction>("C_NGT_"#NAME) FCC0, 835 RC:$fs, RC:$ft), 1>; 836 } 837 838 multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString, 839 Instruction BCFalse, string BCFalseString> { 840 def : MipsInstAlias<!strconcat(BCTrueString, " $offset"), 841 (BCTrue FCC0, brtarget:$offset), 1>; 842 843 def : MipsInstAlias<!strconcat(BCFalseString, " $offset"), 844 (BCFalse FCC0, brtarget:$offset), 1>; 845 } 846 847 let AdditionalPredicates = [NotInMicroMips] in { 848 defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, 849 ISA_MIPS1_NOT_32R6_64R6; 850 defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, 851 ISA_MIPS1_NOT_32R6_64R6, FGR_32; 852 defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, 853 ISA_MIPS1_NOT_32R6_64R6, FGR_64; 854 855 defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6, 856 HARDFLOAT; 857 defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6, 858 HARDFLOAT; 859 } 860 //===----------------------------------------------------------------------===// 861 // Floating Point Patterns 862 //===----------------------------------------------------------------------===// 863 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1; 864 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1; 865 866 def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)), 867 (PseudoCVT_S_W GPR32Opnd:$src)>; 868 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 869 (TRUNC_W_S FGR32Opnd:$src)>, ISA_MIPS1; 870 871 def : MipsPat<(MipsMTC1_D64 GPR32Opnd:$src), 872 (MTC1_D64 GPR32Opnd:$src)>, ISA_MIPS1, FGR_64; 873 874 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 875 (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; 876 let AdditionalPredicates = [NotInMicroMips] in { 877 def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), 878 (TRUNC_W_D32 AFGR64Opnd:$src)>, ISA_MIPS2, FGR_32; 879 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), 880 (CVT_S_D32 AFGR64Opnd:$src)>, ISA_MIPS1, FGR_32; 881 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 882 (CVT_D32_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_32; 883 } 884 885 def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, ISA_MIPS3, GPR_64, FGR_64; 886 def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, ISA_MIPS3, GPR_64, 887 FGR_64; 888 889 def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), 890 (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64; 891 def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), 892 (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64; 893 def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), 894 (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64; 895 896 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 897 (TRUNC_W_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64; 898 def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), 899 (TRUNC_L_S FGR32Opnd:$src)>, ISA_MIPS2, FGR_64; 900 def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), 901 (TRUNC_L_D64 FGR64Opnd:$src)>, ISA_MIPS2, FGR_64; 902 903 let AdditionalPredicates = [NotInMicroMips] in { 904 def : MipsPat<(f32 (fpround FGR64Opnd:$src)), 905 (CVT_S_D64 FGR64Opnd:$src)>, ISA_MIPS1, FGR_64; 906 def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), 907 (CVT_D64_S FGR32Opnd:$src)>, ISA_MIPS1, FGR_64; 908 } 909 910 // To generate NMADD and NMSUB instructions when fneg node is present 911 multiclass NMADD_NMSUB<Instruction Nmadd, Instruction Nmsub, RegisterOperand RC> { 912 def : MipsPat<(fneg (fadd (fmul RC:$fs, RC:$ft), RC:$fr)), 913 (Nmadd RC:$fr, RC:$fs, RC:$ft)>; 914 def : MipsPat<(fneg (fsub (fmul RC:$fs, RC:$ft), RC:$fr)), 915 (Nmsub RC:$fr, RC:$fs, RC:$ft)>; 916 } 917 918 let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in { 919 defm : NMADD_NMSUB<NMADD_S, NMSUB_S, FGR32Opnd>, INSN_MIPS4_32R2_NOT_32R6_64R6; 920 defm : NMADD_NMSUB<NMADD_D32, NMSUB_D32, AFGR64Opnd>, FGR_32, INSN_MIPS4_32R2_NOT_32R6_64R6; 921 defm : NMADD_NMSUB<NMADD_D64, NMSUB_D64, FGR64Opnd>, FGR_64, INSN_MIPS4_32R2_NOT_32R6_64R6; 922 } 923 924 // Patterns for loads/stores with a reg+imm operand. 925 let AdditionalPredicates = [NotInMicroMips] in { 926 let AddedComplexity = 40 in { 927 def : LoadRegImmPat<LWC1, f32, load>, ISA_MIPS1; 928 def : StoreRegImmPat<SWC1, f32>, ISA_MIPS1; 929 930 def : LoadRegImmPat<LDC164, f64, load>, ISA_MIPS1, FGR_64; 931 def : StoreRegImmPat<SDC164, f64>, ISA_MIPS1, FGR_64; 932 933 def : LoadRegImmPat<LDC1, f64, load>, ISA_MIPS1, FGR_32; 934 def : StoreRegImmPat<SDC1, f64>, ISA_MIPS1, FGR_32; 935 } 936 } 937
