1 //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes Mips MSA ASE instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; 15 def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 16 SDTCisInt<1>, 17 SDTCisSameAs<1, 2>, 18 SDTCisVT<3, OtherVT>]>; 19 def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, 20 SDTCisFP<1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisVT<3, OtherVT>]>; 23 def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, 24 SDTCisInt<1>, SDTCisVec<1>, 25 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; 26 def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 27 SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; 28 def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, 29 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; 30 def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 31 SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, 32 SDTCisVT<4, i32>]>; 33 34 def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; 35 def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; 36 def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; 37 def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; 38 def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, 39 [SDNPCommutative, SDNPAssociative]>; 40 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; 41 def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; 42 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; 43 def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; 44 def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; 45 def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; 46 def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; 47 def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; 48 def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; 49 def MipsFMS : SDNode<"MipsISD::FMS", SDTFPTernaryOp>; 50 51 def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; 52 def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; 53 54 def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", 55 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 56 def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", 57 SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; 58 59 def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; 60 def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; 61 def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; 62 def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; 63 64 // Operands 65 66 def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; 67 68 // Pattern fragments 69 def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), 70 (MipsVExtractSExt node:$vec, node:$idx, i8)>; 71 def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), 72 (MipsVExtractSExt node:$vec, node:$idx, i16)>; 73 def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), 74 (MipsVExtractSExt node:$vec, node:$idx, i32)>; 75 def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), 76 (MipsVExtractSExt node:$vec, node:$idx, i64)>; 77 78 def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), 79 (MipsVExtractZExt node:$vec, node:$idx, i8)>; 80 def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), 81 (MipsVExtractZExt node:$vec, node:$idx, i16)>; 82 def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), 83 (MipsVExtractZExt node:$vec, node:$idx, i32)>; 84 def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), 85 (MipsVExtractZExt node:$vec, node:$idx, i64)>; 86 87 def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), 88 (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; 89 def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), 90 (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; 91 def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), 92 (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; 93 def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), 94 (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; 95 96 def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 97 (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 98 def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 99 (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 100 def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 101 (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 102 def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), 103 (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; 104 105 class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : 106 PatFrag<(ops node:$lhs, node:$rhs), 107 (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; 108 109 // ISD::SETFALSE cannot occur 110 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; 111 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; 112 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; 113 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; 114 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 115 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; 116 def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; 117 def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; 118 def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; 119 def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; 120 def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; 121 def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; 122 def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; 123 def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; 124 def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; 125 def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; 126 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; 127 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; 128 def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; 129 def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; 130 def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; 131 def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; 132 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; 133 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; 134 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; 135 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; 136 def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; 137 def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; 138 // ISD::SETTRUE cannot occur 139 // ISD::SETFALSE2 cannot occur 140 // ISD::SETTRUE2 cannot occur 141 142 class vsetcc_type<ValueType ResTy, CondCode CC> : 143 PatFrag<(ops node:$lhs, node:$rhs), 144 (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; 145 146 def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; 147 def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; 148 def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; 149 def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; 150 def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; 151 def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; 152 def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; 153 def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; 154 def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; 155 def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; 156 def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; 157 def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; 158 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; 159 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; 160 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; 161 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; 162 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; 163 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; 164 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; 165 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; 166 167 def vsplati8 : PatFrag<(ops node:$e0), 168 (v16i8 (build_vector node:$e0, node:$e0, 169 node:$e0, node:$e0, 170 node:$e0, node:$e0, 171 node:$e0, node:$e0, 172 node:$e0, node:$e0, 173 node:$e0, node:$e0, 174 node:$e0, node:$e0, 175 node:$e0, node:$e0))>; 176 def vsplati16 : PatFrag<(ops node:$e0), 177 (v8i16 (build_vector node:$e0, node:$e0, 178 node:$e0, node:$e0, 179 node:$e0, node:$e0, 180 node:$e0, node:$e0))>; 181 def vsplati32 : PatFrag<(ops node:$e0), 182 (v4i32 (build_vector node:$e0, node:$e0, 183 node:$e0, node:$e0))>; 184 185 def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 186 APInt Imm; 187 SDNode *BV = N->getOperand(0).getNode(); 188 EVT EltTy = N->getValueType(0).getVectorElementType(); 189 190 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 191 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 192 }]>; 193 194 def vsplati64 : PatFrag<(ops node:$e0), 195 (v2i64 (build_vector node:$e0, node:$e0))>; 196 197 def vsplati64_splat_d : PatFrag<(ops node:$e0), 198 (v2i64 (bitconvert 199 (v4i32 (and 200 (v4i32 (build_vector node:$e0, 201 node:$e0, 202 node:$e0, 203 node:$e0)), 204 vsplati64_imm_eq_1))))>; 205 206 def vsplatf32 : PatFrag<(ops node:$e0), 207 (v4f32 (build_vector node:$e0, node:$e0, 208 node:$e0, node:$e0))>; 209 def vsplatf64 : PatFrag<(ops node:$e0), 210 (v2f64 (build_vector node:$e0, node:$e0))>; 211 212 def vsplati8_elt : PatFrag<(ops node:$v, node:$i), 213 (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; 214 def vsplati16_elt : PatFrag<(ops node:$v, node:$i), 215 (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; 216 def vsplati32_elt : PatFrag<(ops node:$v, node:$i), 217 (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; 218 def vsplati64_elt : PatFrag<(ops node:$v, node:$i), 219 (MipsVSHF (vsplati64_splat_d node:$i), 220 node:$v, node:$v)>; 221 222 class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], 223 SDNodeXForm xform = NOOP_SDNodeXForm> 224 : PatLeaf<frag, pred, xform> { 225 Operand OpClass = opclass; 226 } 227 228 class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, 229 list<SDNode> roots = [], 230 list<SDNodeProperty> props = []> : 231 ComplexPattern<ty, numops, fn, roots, props> { 232 Operand OpClass = opclass; 233 } 234 235 def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, 236 "selectVSplatUimm3", 237 [build_vector, bitconvert]>; 238 239 def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, 240 "selectVSplatUimm4", 241 [build_vector, bitconvert]>; 242 243 def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, 244 "selectVSplatUimm5", 245 [build_vector, bitconvert]>; 246 247 def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, 248 "selectVSplatUimm8", 249 [build_vector, bitconvert]>; 250 251 def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, 252 "selectVSplatSimm5", 253 [build_vector, bitconvert]>; 254 255 def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, 256 "selectVSplatUimm3", 257 [build_vector, bitconvert]>; 258 259 def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, 260 "selectVSplatUimm4", 261 [build_vector, bitconvert]>; 262 263 def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, 264 "selectVSplatUimm5", 265 [build_vector, bitconvert]>; 266 267 def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, 268 "selectVSplatSimm5", 269 [build_vector, bitconvert]>; 270 271 def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, 272 "selectVSplatUimm2", 273 [build_vector, bitconvert]>; 274 275 def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, 276 "selectVSplatUimm5", 277 [build_vector, bitconvert]>; 278 279 def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, 280 "selectVSplatSimm5", 281 [build_vector, bitconvert]>; 282 283 def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, 284 "selectVSplatUimm1", 285 [build_vector, bitconvert]>; 286 287 def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, 288 "selectVSplatUimm5", 289 [build_vector, bitconvert]>; 290 291 def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, 292 "selectVSplatUimm6", 293 [build_vector, bitconvert]>; 294 295 def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, 296 "selectVSplatSimm5", 297 [build_vector, bitconvert]>; 298 299 // Any build_vector that is a constant splat with a value that is an exact 300 // power of 2 301 def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", 302 [build_vector, bitconvert]>; 303 304 // Any build_vector that is a constant splat with a value that is the bitwise 305 // inverse of an exact power of 2 306 def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", 307 [build_vector, bitconvert]>; 308 309 // Any build_vector that is a constant splat with only a consecutive sequence 310 // of left-most bits set. 311 def vsplat_maskl_bits_uimm3 312 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL", 313 [build_vector, bitconvert]>; 314 def vsplat_maskl_bits_uimm4 315 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL", 316 [build_vector, bitconvert]>; 317 def vsplat_maskl_bits_uimm5 318 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL", 319 [build_vector, bitconvert]>; 320 def vsplat_maskl_bits_uimm6 321 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL", 322 [build_vector, bitconvert]>; 323 324 // Any build_vector that is a constant splat with only a consecutive sequence 325 // of right-most bits set. 326 def vsplat_maskr_bits_uimm3 327 : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR", 328 [build_vector, bitconvert]>; 329 def vsplat_maskr_bits_uimm4 330 : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR", 331 [build_vector, bitconvert]>; 332 def vsplat_maskr_bits_uimm5 333 : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR", 334 [build_vector, bitconvert]>; 335 def vsplat_maskr_bits_uimm6 336 : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR", 337 [build_vector, bitconvert]>; 338 339 // Any build_vector that is a constant splat with a value that equals 1 340 // FIXME: These should be a ComplexPattern but we can't use them because the 341 // ISel generator requires the uses to have a name, but providing a name 342 // causes other errors ("used in pattern but not operand list") 343 def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ 344 APInt Imm; 345 EVT EltTy = N->getValueType(0).getVectorElementType(); 346 347 return selectVSplat(N, Imm, EltTy.getSizeInBits()) && 348 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; 349 }]>; 350 351 def vbclr_b : PatFrag<(ops node:$ws, node:$wt), 352 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 353 immAllOnesV))>; 354 def vbclr_h : PatFrag<(ops node:$ws, node:$wt), 355 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 356 immAllOnesV))>; 357 def vbclr_w : PatFrag<(ops node:$ws, node:$wt), 358 (and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt), 359 immAllOnesV))>; 360 def vbclr_d : PatFrag<(ops node:$ws, node:$wt), 361 (and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 362 node:$wt), 363 (bitconvert (v4i32 immAllOnesV))))>; 364 365 def vbneg_b : PatFrag<(ops node:$ws, node:$wt), 366 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 367 def vbneg_h : PatFrag<(ops node:$ws, node:$wt), 368 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 369 def vbneg_w : PatFrag<(ops node:$ws, node:$wt), 370 (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 371 def vbneg_d : PatFrag<(ops node:$ws, node:$wt), 372 (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 373 node:$wt))>; 374 375 def vbset_b : PatFrag<(ops node:$ws, node:$wt), 376 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 377 def vbset_h : PatFrag<(ops node:$ws, node:$wt), 378 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 379 def vbset_w : PatFrag<(ops node:$ws, node:$wt), 380 (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; 381 def vbset_d : PatFrag<(ops node:$ws, node:$wt), 382 (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), 383 node:$wt))>; 384 385 def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), 386 (add node:$wd, (mul node:$ws, node:$wt))>; 387 388 def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), 389 (sub node:$wd, (mul node:$ws, node:$wt))>; 390 391 def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), 392 (fmul node:$ws, (fexp2 node:$wt))>; 393 394 // Instruction encoding. 395 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; 396 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; 397 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; 398 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; 399 400 class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; 401 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; 402 class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; 403 class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; 404 405 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; 406 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; 407 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; 408 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; 409 410 class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; 411 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; 412 class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; 413 class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; 414 415 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; 416 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; 417 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; 418 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; 419 420 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; 421 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; 422 class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; 423 class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; 424 425 class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; 426 427 class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; 428 429 class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; 430 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; 431 class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; 432 class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; 433 434 class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; 435 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; 436 class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; 437 class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; 438 439 class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; 440 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; 441 class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; 442 class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; 443 444 class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; 445 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; 446 class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; 447 class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; 448 449 class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; 450 class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; 451 class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; 452 class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; 453 454 class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; 455 class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; 456 class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; 457 class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; 458 459 class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; 460 class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; 461 class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; 462 class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; 463 464 class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; 465 class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; 466 class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; 467 class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; 468 469 class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; 470 class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; 471 class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; 472 class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; 473 474 class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; 475 class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; 476 class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; 477 class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; 478 479 class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; 480 class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; 481 class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; 482 class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; 483 484 class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; 485 class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; 486 class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; 487 class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; 488 489 class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; 490 491 class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; 492 493 class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; 494 495 class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; 496 497 class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; 498 class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; 499 class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; 500 class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; 501 502 class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; 503 class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; 504 class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; 505 class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; 506 507 class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; 508 class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; 509 class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; 510 class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; 511 512 class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; 513 514 class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; 515 516 class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; 517 518 class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; 519 class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; 520 class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; 521 class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; 522 523 class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; 524 class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; 525 class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; 526 class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; 527 528 class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; 529 class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; 530 class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; 531 class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; 532 533 class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; 534 535 class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; 536 class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; 537 class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; 538 class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; 539 540 class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; 541 class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; 542 class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; 543 class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; 544 545 class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; 546 547 class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; 548 class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; 549 class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; 550 class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; 551 552 class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; 553 class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; 554 class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; 555 class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; 556 557 class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; 558 class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; 559 class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; 560 class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; 561 562 class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; 563 class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; 564 class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; 565 class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; 566 567 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; 568 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; 569 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; 570 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; 571 572 class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; 573 class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; 574 class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; 575 class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; 576 577 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; 578 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; 579 class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; 580 class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; 581 582 class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; 583 class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; 584 class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; 585 class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; 586 587 class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; 588 class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; 589 class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; 590 class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; 591 592 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; 593 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; 594 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; 595 596 class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; 597 598 class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; 599 class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; 600 class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; 601 class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; 602 603 class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; 604 class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; 605 class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; 606 class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; 607 608 class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; 609 class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; 610 class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; 611 612 class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; 613 class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; 614 class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; 615 616 class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; 617 class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; 618 class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; 619 620 class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; 621 class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; 622 class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; 623 624 class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; 625 class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; 626 class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; 627 628 class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; 629 class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; 630 class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; 631 632 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; 633 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; 634 635 class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; 636 class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; 637 638 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; 639 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; 640 641 class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; 642 class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; 643 644 class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; 645 class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; 646 647 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; 648 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; 649 650 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; 651 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; 652 653 class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; 654 class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; 655 656 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; 657 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; 658 659 class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; 660 class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; 661 662 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; 663 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; 664 665 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; 666 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; 667 668 class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; 669 class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; 670 671 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; 672 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; 673 674 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; 675 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; 676 677 class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; 678 class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; 679 680 class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; 681 class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; 682 683 class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; 684 class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; 685 686 class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; 687 class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; 688 689 class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; 690 class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; 691 692 class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; 693 class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; 694 695 class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; 696 class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; 697 698 class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; 699 class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; 700 class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; 701 class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; 702 703 class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; 704 class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; 705 706 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; 707 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; 708 709 class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; 710 class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; 711 712 class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; 713 class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; 714 715 class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; 716 class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; 717 718 class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; 719 class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; 720 721 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; 722 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; 723 724 class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; 725 class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; 726 727 class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; 728 class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; 729 730 class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; 731 class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; 732 733 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; 734 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; 735 736 class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; 737 class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; 738 739 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; 740 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; 741 742 class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; 743 class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; 744 745 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; 746 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; 747 748 class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; 749 class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; 750 751 class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; 752 class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; 753 754 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; 755 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; 756 757 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; 758 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; 759 760 class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; 761 class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; 762 763 class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; 764 class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; 765 766 class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; 767 class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; 768 769 class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; 770 class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; 771 772 class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; 773 class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; 774 775 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; 776 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; 777 778 class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; 779 class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; 780 781 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; 782 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; 783 784 class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; 785 class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; 786 787 class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; 788 class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; 789 790 class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; 791 class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; 792 class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; 793 794 class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; 795 class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; 796 class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; 797 798 class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; 799 class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; 800 class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; 801 802 class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; 803 class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; 804 class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; 805 806 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; 807 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; 808 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; 809 class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; 810 811 class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; 812 class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; 813 class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; 814 class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; 815 816 class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; 817 class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; 818 class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; 819 class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; 820 821 class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; 822 class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; 823 class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; 824 class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; 825 826 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; 827 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; 828 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; 829 class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; 830 831 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; 832 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; 833 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; 834 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; 835 836 class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; 837 class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; 838 class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; 839 class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; 840 841 class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; 842 class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; 843 class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; 844 class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; 845 846 class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; 847 class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; 848 849 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; 850 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; 851 852 class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; 853 class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; 854 855 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; 856 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; 857 class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; 858 class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; 859 860 class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; 861 class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; 862 class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; 863 class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; 864 865 class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; 866 class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; 867 class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; 868 class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; 869 870 class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; 871 class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; 872 class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; 873 class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; 874 875 class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; 876 class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; 877 class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; 878 class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; 879 880 class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; 881 class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; 882 class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; 883 class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; 884 885 class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; 886 class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; 887 class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; 888 class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; 889 890 class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; 891 class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; 892 class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; 893 class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; 894 895 class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; 896 class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; 897 class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; 898 class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; 899 900 class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; 901 class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; 902 class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; 903 class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; 904 905 class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; 906 class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; 907 class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; 908 class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; 909 910 class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; 911 class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; 912 class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; 913 class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; 914 915 class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; 916 class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; 917 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; 918 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; 919 920 class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; 921 922 class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; 923 class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; 924 925 class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; 926 class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; 927 928 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; 929 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; 930 class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; 931 class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; 932 933 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; 934 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; 935 936 class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; 937 class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; 938 939 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; 940 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; 941 class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; 942 class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; 943 944 class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; 945 class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; 946 class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; 947 class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; 948 949 class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; 950 class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; 951 class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; 952 class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; 953 954 class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; 955 956 class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; 957 958 class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; 959 960 class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; 961 962 class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; 963 class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; 964 class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; 965 class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; 966 967 class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; 968 class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; 969 class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; 970 class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; 971 972 class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; 973 class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; 974 class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; 975 class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; 976 977 class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; 978 class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; 979 class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; 980 class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; 981 982 class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; 983 class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; 984 class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; 985 class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; 986 987 class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; 988 class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; 989 class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; 990 991 class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; 992 class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; 993 class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; 994 class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; 995 996 class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; 997 class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; 998 class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; 999 class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; 1000 1001 class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; 1002 class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; 1003 class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; 1004 class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; 1005 1006 class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; 1007 class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; 1008 class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; 1009 class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; 1010 1011 class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; 1012 class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; 1013 class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; 1014 class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; 1015 1016 class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; 1017 class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; 1018 class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; 1019 class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; 1020 1021 class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; 1022 class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; 1023 class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; 1024 class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; 1025 1026 class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; 1027 class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; 1028 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; 1029 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; 1030 1031 class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; 1032 class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; 1033 class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; 1034 class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; 1035 1036 class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; 1037 class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; 1038 class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; 1039 class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; 1040 1041 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; 1042 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; 1043 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; 1044 class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; 1045 1046 class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; 1047 class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; 1048 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; 1049 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; 1050 1051 class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; 1052 class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; 1053 class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; 1054 class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; 1055 1056 class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; 1057 class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; 1058 class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; 1059 class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; 1060 1061 class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; 1062 class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; 1063 class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; 1064 class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; 1065 1066 class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; 1067 class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; 1068 class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; 1069 class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; 1070 1071 class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; 1072 class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; 1073 class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; 1074 class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; 1075 1076 class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; 1077 class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; 1078 class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; 1079 class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; 1080 1081 class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; 1082 class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; 1083 class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; 1084 class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; 1085 1086 class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; 1087 class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; 1088 class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; 1089 class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; 1090 1091 class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; 1092 class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; 1093 class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; 1094 class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; 1095 1096 class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; 1097 class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; 1098 class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; 1099 class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; 1100 1101 class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; 1102 1103 class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; 1104 1105 // Instruction desc. 1106 class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1107 ComplexPattern Imm, RegisterOperand ROWD, 1108 RegisterOperand ROWS = ROWD, 1109 InstrItinClass itin = NoItinerary> { 1110 dag OutOperandList = (outs ROWD:$wd); 1111 dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); 1112 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1113 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1114 InstrItinClass Itinerary = itin; 1115 } 1116 1117 class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1118 ComplexPattern Imm, RegisterOperand ROWD, 1119 RegisterOperand ROWS = ROWD, 1120 InstrItinClass itin = NoItinerary> { 1121 dag OutOperandList = (outs ROWD:$wd); 1122 dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); 1123 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1124 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1125 InstrItinClass Itinerary = itin; 1126 } 1127 1128 class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1129 ComplexPattern Imm, RegisterOperand ROWD, 1130 RegisterOperand ROWS = ROWD, 1131 InstrItinClass itin = NoItinerary> { 1132 dag OutOperandList = (outs ROWD:$wd); 1133 dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); 1134 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1135 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1136 InstrItinClass Itinerary = itin; 1137 } 1138 1139 class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1140 ComplexPattern Imm, RegisterOperand ROWD, 1141 RegisterOperand ROWS = ROWD, 1142 InstrItinClass itin = NoItinerary> { 1143 dag OutOperandList = (outs ROWD:$wd); 1144 dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); 1145 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1146 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1147 InstrItinClass Itinerary = itin; 1148 } 1149 1150 class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1151 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1152 RegisterOperand ROWS = ROWD, 1153 InstrItinClass itin = NoItinerary> { 1154 dag OutOperandList = (outs ROWD:$wd); 1155 dag InOperandList = (ins ROWS:$ws, ImmOp:$m); 1156 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1157 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; 1158 InstrItinClass Itinerary = itin; 1159 } 1160 1161 class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, 1162 SplatComplexPattern Mask, RegisterOperand ROWD, 1163 RegisterOperand ROWS = ROWD, 1164 InstrItinClass itin = NoItinerary> { 1165 dag OutOperandList = (outs ROWD:$wd); 1166 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m); 1167 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1168 // Note that binsxi and vselect treat the condition operand the opposite 1169 // way to each other. 1170 // (vselect cond, if_set, if_clear) 1171 // (BSEL_V cond, if_clear, if_set) 1172 list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), 1173 ROWS:$wd_in))]; 1174 InstrItinClass Itinerary = itin; 1175 string Constraints = "$wd = $wd_in"; 1176 } 1177 1178 class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, 1179 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1180 RegisterOperand ROWS = ROWD, 1181 InstrItinClass itin = NoItinerary> : 1182 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1183 1184 class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, 1185 SplatComplexPattern ImmOp, RegisterOperand ROWD, 1186 RegisterOperand ROWS = ROWD, 1187 InstrItinClass itin = NoItinerary> : 1188 MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; 1189 1190 class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1191 SplatComplexPattern SplatImm, 1192 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1193 InstrItinClass itin = NoItinerary> { 1194 dag OutOperandList = (outs ROWD:$wd); 1195 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); 1196 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); 1197 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; 1198 InstrItinClass Itinerary = itin; 1199 } 1200 1201 class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1202 ValueType VecTy, Operand ImmOp, ImmLeaf Imm, 1203 RegisterOperand ROD, RegisterOperand ROWS, 1204 InstrItinClass itin = NoItinerary> { 1205 dag OutOperandList = (outs ROD:$rd); 1206 dag InOperandList = (ins ROWS:$ws, ImmOp:$n); 1207 string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); 1208 list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))]; 1209 InstrItinClass Itinerary = itin; 1210 } 1211 1212 class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1213 RegisterOperand ROWD, RegisterOperand ROWS, 1214 Operand ImmOp, ImmLeaf Imm, 1215 InstrItinClass itin = NoItinerary> { 1216 dag OutOperandList = (outs ROWD:$wd); 1217 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n); 1218 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1219 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1220 Imm:$n))]; 1221 string Constraints = "$wd = $wd_in"; 1222 InstrItinClass Itinerary = itin; 1223 } 1224 1225 class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, 1226 Operand ImmOp, ImmLeaf Imm, RegisterClass RCD, 1227 RegisterClass RCWS> : 1228 MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n), 1229 [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> { 1230 bit usesCustomInserter = 1; 1231 } 1232 1233 class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1234 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1235 RegisterOperand ROWS = ROWD, 1236 InstrItinClass itin = NoItinerary> { 1237 dag OutOperandList = (outs ROWD:$wd); 1238 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); 1239 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); 1240 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; 1241 InstrItinClass Itinerary = itin; 1242 } 1243 1244 class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1245 SplatComplexPattern SplatImm, RegisterOperand ROWD, 1246 RegisterOperand ROWS = ROWD, 1247 InstrItinClass itin = NoItinerary> { 1248 dag OutOperandList = (outs ROWD:$wd); 1249 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); 1250 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1251 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; 1252 InstrItinClass Itinerary = itin; 1253 } 1254 1255 class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1256 RegisterOperand ROWS = ROWD, 1257 InstrItinClass itin = NoItinerary> { 1258 dag OutOperandList = (outs ROWD:$wd); 1259 dag InOperandList = (ins ROWS:$ws, uimm8:$u8); 1260 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); 1261 list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))]; 1262 InstrItinClass Itinerary = itin; 1263 } 1264 1265 class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1266 InstrItinClass itin = NoItinerary> { 1267 dag OutOperandList = (outs ROWD:$wd); 1268 dag InOperandList = (ins vsplat_simm10:$s10); 1269 string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); 1270 // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp 1271 list<dag> Pattern = []; 1272 bit hasSideEffects = 0; 1273 InstrItinClass Itinerary = itin; 1274 } 1275 1276 class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1277 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1278 InstrItinClass itin = NoItinerary> { 1279 dag OutOperandList = (outs ROWD:$wd); 1280 dag InOperandList = (ins ROWS:$ws); 1281 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1282 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1283 InstrItinClass Itinerary = itin; 1284 } 1285 1286 class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, 1287 SDPatternOperator OpNode, RegisterOperand ROWD, 1288 RegisterOperand ROS = ROWD, 1289 InstrItinClass itin = NoItinerary> { 1290 dag OutOperandList = (outs ROWD:$wd); 1291 dag InOperandList = (ins ROS:$rs); 1292 string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); 1293 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; 1294 InstrItinClass Itinerary = itin; 1295 } 1296 1297 class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode, 1298 RegisterClass RCWD, RegisterClass RCWS = RCWD> : 1299 MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), 1300 [(set RCWD:$wd, (OpNode RCWS:$fs))]> { 1301 let usesCustomInserter = 1; 1302 } 1303 1304 class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1305 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1306 InstrItinClass itin = NoItinerary> { 1307 dag OutOperandList = (outs ROWD:$wd); 1308 dag InOperandList = (ins ROWS:$ws); 1309 string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); 1310 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; 1311 InstrItinClass Itinerary = itin; 1312 } 1313 1314 class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1315 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1316 RegisterOperand ROWT = ROWD, 1317 InstrItinClass itin = NoItinerary> { 1318 dag OutOperandList = (outs ROWD:$wd); 1319 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1320 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1321 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1322 InstrItinClass Itinerary = itin; 1323 } 1324 1325 class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1326 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1327 RegisterOperand ROWT = ROWD, 1328 InstrItinClass itin = NoItinerary> { 1329 dag OutOperandList = (outs ROWD:$wd); 1330 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1331 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1332 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1333 ROWT:$wt))]; 1334 string Constraints = "$wd = $wd_in"; 1335 InstrItinClass Itinerary = itin; 1336 } 1337 1338 class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1339 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1340 InstrItinClass itin = NoItinerary> { 1341 dag OutOperandList = (outs ROWD:$wd); 1342 dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); 1343 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1344 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; 1345 InstrItinClass Itinerary = itin; 1346 } 1347 1348 class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, 1349 RegisterOperand ROWS = ROWD, 1350 RegisterOperand ROWT = ROWD, 1351 InstrItinClass itin = NoItinerary> { 1352 dag OutOperandList = (outs ROWD:$wd); 1353 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1354 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1355 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, 1356 ROWT:$wt))]; 1357 string Constraints = "$wd = $wd_in"; 1358 InstrItinClass Itinerary = itin; 1359 } 1360 1361 class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1362 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1363 InstrItinClass itin = NoItinerary> { 1364 dag OutOperandList = (outs ROWD:$wd); 1365 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); 1366 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); 1367 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1368 GPR32Opnd:$rt))]; 1369 InstrItinClass Itinerary = itin; 1370 string Constraints = "$wd = $wd_in"; 1371 } 1372 1373 class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1374 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1375 RegisterOperand ROWT = ROWD, 1376 InstrItinClass itin = NoItinerary> { 1377 dag OutOperandList = (outs ROWD:$wd); 1378 dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); 1379 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1380 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, 1381 ROWT:$wt))]; 1382 InstrItinClass Itinerary = itin; 1383 string Constraints = "$wd = $wd_in"; 1384 } 1385 1386 class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1387 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1388 RegisterOperand ROWT = ROWD, 1389 InstrItinClass itin = NoItinerary> : 1390 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1391 1392 class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1393 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1394 RegisterOperand ROWT = ROWD, 1395 InstrItinClass itin = NoItinerary> : 1396 MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; 1397 1398 class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { 1399 dag OutOperandList = (outs); 1400 dag InOperandList = (ins ROWD:$wt, brtarget:$offset); 1401 string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); 1402 list<dag> Pattern = []; 1403 InstrItinClass Itinerary = NoItinerary; 1404 bit isBranch = 1; 1405 bit isTerminator = 1; 1406 bit hasDelaySlot = 1; 1407 list<Register> Defs = [AT]; 1408 } 1409 1410 class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1411 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1412 RegisterOperand ROS, 1413 InstrItinClass itin = NoItinerary> { 1414 dag OutOperandList = (outs ROWD:$wd); 1415 dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n); 1416 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); 1417 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))]; 1418 InstrItinClass Itinerary = itin; 1419 string Constraints = "$wd = $wd_in"; 1420 } 1421 1422 class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1423 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1424 RegisterOperand ROFS> : 1425 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs), 1426 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> { 1427 bit usesCustomInserter = 1; 1428 string Constraints = "$wd = $wd_in"; 1429 } 1430 1431 class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, 1432 RegisterOperand ROWD, RegisterOperand ROFS, 1433 RegisterOperand ROIdx> : 1434 MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), 1435 [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, 1436 ROIdx:$n))]> { 1437 bit usesCustomInserter = 1; 1438 string Constraints = "$wd = $wd_in"; 1439 } 1440 1441 class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1442 Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, 1443 RegisterOperand ROWS = ROWD, 1444 InstrItinClass itin = NoItinerary> { 1445 dag OutOperandList = (outs ROWD:$wd); 1446 dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2); 1447 string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); 1448 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, 1449 Imm:$n, 1450 ROWS:$ws, 1451 immz:$n2))]; 1452 InstrItinClass Itinerary = itin; 1453 string Constraints = "$wd = $wd_in"; 1454 } 1455 1456 class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 1457 RegisterOperand ROWD, RegisterOperand ROWS = ROWD, 1458 RegisterOperand ROWT = ROWD, 1459 InstrItinClass itin = NoItinerary> { 1460 dag OutOperandList = (outs ROWD:$wd); 1461 dag InOperandList = (ins ROWS:$ws, ROWT:$wt); 1462 string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); 1463 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; 1464 InstrItinClass Itinerary = itin; 1465 } 1466 1467 class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, 1468 RegisterOperand ROWD, 1469 RegisterOperand ROWS = ROWD, 1470 InstrItinClass itin = NoItinerary> { 1471 dag OutOperandList = (outs ROWD:$wd); 1472 dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); 1473 string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); 1474 list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, 1475 ROWS:$ws))]; 1476 InstrItinClass Itinerary = itin; 1477 } 1478 1479 class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, 1480 RegisterOperand ROWS = ROWD, 1481 RegisterOperand ROWT = ROWD> : 1482 MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), 1483 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; 1484 1485 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, 1486 IsCommutable; 1487 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, 1488 IsCommutable; 1489 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, 1490 IsCommutable; 1491 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, 1492 IsCommutable; 1493 1494 class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, 1495 MSA128BOpnd>, IsCommutable; 1496 class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, 1497 MSA128HOpnd>, IsCommutable; 1498 class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, 1499 MSA128WOpnd>, IsCommutable; 1500 class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, 1501 MSA128DOpnd>, IsCommutable; 1502 1503 class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, 1504 MSA128BOpnd>, IsCommutable; 1505 class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, 1506 MSA128HOpnd>, IsCommutable; 1507 class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, 1508 MSA128WOpnd>, IsCommutable; 1509 class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, 1510 MSA128DOpnd>, IsCommutable; 1511 1512 class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, 1513 MSA128BOpnd>, IsCommutable; 1514 class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, 1515 MSA128HOpnd>, IsCommutable; 1516 class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, 1517 MSA128WOpnd>, IsCommutable; 1518 class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, 1519 MSA128DOpnd>, IsCommutable; 1520 1521 class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; 1522 class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; 1523 class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; 1524 class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; 1525 1526 class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, 1527 MSA128BOpnd>; 1528 class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, 1529 MSA128HOpnd>; 1530 class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, 1531 MSA128WOpnd>; 1532 class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, 1533 MSA128DOpnd>; 1534 1535 class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; 1536 class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; 1537 class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; 1538 class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; 1539 1540 class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, 1541 MSA128BOpnd>; 1542 1543 class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, 1544 MSA128BOpnd>; 1545 class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, 1546 MSA128HOpnd>; 1547 class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, 1548 MSA128WOpnd>; 1549 class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, 1550 MSA128DOpnd>; 1551 1552 class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, 1553 MSA128BOpnd>; 1554 class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, 1555 MSA128HOpnd>; 1556 class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, 1557 MSA128WOpnd>; 1558 class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, 1559 MSA128DOpnd>; 1560 1561 class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, 1562 IsCommutable; 1563 class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, 1564 IsCommutable; 1565 class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, 1566 IsCommutable; 1567 class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, 1568 IsCommutable; 1569 1570 class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, 1571 IsCommutable; 1572 class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, 1573 IsCommutable; 1574 class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, 1575 IsCommutable; 1576 class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, 1577 IsCommutable; 1578 1579 class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, 1580 MSA128BOpnd>, IsCommutable; 1581 class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, 1582 MSA128HOpnd>, IsCommutable; 1583 class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, 1584 MSA128WOpnd>, IsCommutable; 1585 class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, 1586 MSA128DOpnd>, IsCommutable; 1587 1588 class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, 1589 MSA128BOpnd>, IsCommutable; 1590 class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, 1591 MSA128HOpnd>, IsCommutable; 1592 class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, 1593 MSA128WOpnd>, IsCommutable; 1594 class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, 1595 MSA128DOpnd>, IsCommutable; 1596 1597 class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; 1598 class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; 1599 class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; 1600 class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; 1601 1602 class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, 1603 MSA128BOpnd>; 1604 class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, 1605 MSA128HOpnd>; 1606 class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, 1607 MSA128WOpnd>; 1608 class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, 1609 MSA128DOpnd>; 1610 1611 class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, 1612 MSA128BOpnd>; 1613 class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, 1614 MSA128HOpnd>; 1615 class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, 1616 MSA128WOpnd>; 1617 class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, 1618 MSA128DOpnd>; 1619 1620 class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>; 1621 class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>; 1622 class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>; 1623 class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>; 1624 1625 class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, 1626 MSA128BOpnd>; 1627 class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, 1628 MSA128HOpnd>; 1629 class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, 1630 MSA128WOpnd>; 1631 class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, 1632 MSA128DOpnd>; 1633 1634 class BINSRI_B_DESC 1635 : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3, 1636 MSA128BOpnd>; 1637 class BINSRI_H_DESC 1638 : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4, 1639 MSA128HOpnd>; 1640 class BINSRI_W_DESC 1641 : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5, 1642 MSA128WOpnd>; 1643 class BINSRI_D_DESC 1644 : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6, 1645 MSA128DOpnd>; 1646 1647 class BMNZ_V_DESC { 1648 dag OutOperandList = (outs MSA128BOpnd:$wd); 1649 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1650 MSA128BOpnd:$wt); 1651 string AsmString = "bmnz.v\t$wd, $ws, $wt"; 1652 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1653 MSA128BOpnd:$ws, 1654 MSA128BOpnd:$wd_in))]; 1655 InstrItinClass Itinerary = NoItinerary; 1656 string Constraints = "$wd = $wd_in"; 1657 } 1658 1659 class BMNZI_B_DESC { 1660 dag OutOperandList = (outs MSA128BOpnd:$wd); 1661 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1662 vsplat_uimm8:$u8); 1663 string AsmString = "bmnzi.b\t$wd, $ws, $u8"; 1664 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1665 MSA128BOpnd:$ws, 1666 MSA128BOpnd:$wd_in))]; 1667 InstrItinClass Itinerary = NoItinerary; 1668 string Constraints = "$wd = $wd_in"; 1669 } 1670 1671 class BMZ_V_DESC { 1672 dag OutOperandList = (outs MSA128BOpnd:$wd); 1673 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1674 MSA128BOpnd:$wt); 1675 string AsmString = "bmz.v\t$wd, $ws, $wt"; 1676 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, 1677 MSA128BOpnd:$wd_in, 1678 MSA128BOpnd:$ws))]; 1679 InstrItinClass Itinerary = NoItinerary; 1680 string Constraints = "$wd = $wd_in"; 1681 } 1682 1683 class BMZI_B_DESC { 1684 dag OutOperandList = (outs MSA128BOpnd:$wd); 1685 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1686 vsplat_uimm8:$u8); 1687 string AsmString = "bmzi.b\t$wd, $ws, $u8"; 1688 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, 1689 MSA128BOpnd:$wd_in, 1690 MSA128BOpnd:$ws))]; 1691 InstrItinClass Itinerary = NoItinerary; 1692 string Constraints = "$wd = $wd_in"; 1693 } 1694 1695 class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; 1696 class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; 1697 class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; 1698 class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; 1699 1700 class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, 1701 MSA128BOpnd>; 1702 class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, 1703 MSA128HOpnd>; 1704 class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, 1705 MSA128WOpnd>; 1706 class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, 1707 MSA128DOpnd>; 1708 1709 class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; 1710 class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; 1711 class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; 1712 class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; 1713 1714 class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; 1715 1716 class BSEL_V_DESC { 1717 dag OutOperandList = (outs MSA128BOpnd:$wd); 1718 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1719 MSA128BOpnd:$wt); 1720 string AsmString = "bsel.v\t$wd, $ws, $wt"; 1721 // Note that vselect and BSEL_V treat the condition operand the opposite way 1722 // from each other. 1723 // (vselect cond, if_set, if_clear) 1724 // (BSEL_V cond, if_clear, if_set) 1725 list<dag> Pattern = [(set MSA128BOpnd:$wd, 1726 (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, 1727 MSA128BOpnd:$ws))]; 1728 InstrItinClass Itinerary = NoItinerary; 1729 string Constraints = "$wd = $wd_in"; 1730 } 1731 1732 class BSELI_B_DESC { 1733 dag OutOperandList = (outs MSA128BOpnd:$wd); 1734 dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, 1735 vsplat_uimm8:$u8); 1736 string AsmString = "bseli.b\t$wd, $ws, $u8"; 1737 // Note that vselect and BSEL_V treat the condition operand the opposite way 1738 // from each other. 1739 // (vselect cond, if_set, if_clear) 1740 // (BSEL_V cond, if_clear, if_set) 1741 list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, 1742 vsplati8_uimm8:$u8, 1743 MSA128BOpnd:$ws))]; 1744 InstrItinClass Itinerary = NoItinerary; 1745 string Constraints = "$wd = $wd_in"; 1746 } 1747 1748 class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; 1749 class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; 1750 class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; 1751 class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; 1752 1753 class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, 1754 MSA128BOpnd>; 1755 class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, 1756 MSA128HOpnd>; 1757 class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, 1758 MSA128WOpnd>; 1759 class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, 1760 MSA128DOpnd>; 1761 1762 class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; 1763 class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; 1764 class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; 1765 class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; 1766 1767 class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; 1768 1769 class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, 1770 IsCommutable; 1771 class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, 1772 IsCommutable; 1773 class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, 1774 IsCommutable; 1775 class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, 1776 IsCommutable; 1777 1778 class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, 1779 MSA128BOpnd>; 1780 class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, 1781 MSA128HOpnd>; 1782 class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, 1783 MSA128WOpnd>; 1784 class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, 1785 MSA128DOpnd>; 1786 1787 class CFCMSA_DESC { 1788 dag OutOperandList = (outs GPR32Opnd:$rd); 1789 dag InOperandList = (ins MSA128CROpnd:$cs); 1790 string AsmString = "cfcmsa\t$rd, $cs"; 1791 InstrItinClass Itinerary = NoItinerary; 1792 bit hasSideEffects = 1; 1793 bit isMoveReg = 1; 1794 } 1795 1796 class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; 1797 class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; 1798 class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; 1799 class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; 1800 1801 class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; 1802 class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; 1803 class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; 1804 class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; 1805 1806 class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, 1807 vsplati8_simm5, MSA128BOpnd>; 1808 class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, 1809 vsplati16_simm5, MSA128HOpnd>; 1810 class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, 1811 vsplati32_simm5, MSA128WOpnd>; 1812 class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, 1813 vsplati64_simm5, MSA128DOpnd>; 1814 1815 class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, 1816 vsplati8_uimm5, MSA128BOpnd>; 1817 class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, 1818 vsplati16_uimm5, MSA128HOpnd>; 1819 class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, 1820 vsplati32_uimm5, MSA128WOpnd>; 1821 class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, 1822 vsplati64_uimm5, MSA128DOpnd>; 1823 1824 class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; 1825 class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; 1826 class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; 1827 class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; 1828 1829 class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; 1830 class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; 1831 class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; 1832 class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; 1833 1834 class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, 1835 vsplati8_simm5, MSA128BOpnd>; 1836 class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, 1837 vsplati16_simm5, MSA128HOpnd>; 1838 class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, 1839 vsplati32_simm5, MSA128WOpnd>; 1840 class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, 1841 vsplati64_simm5, MSA128DOpnd>; 1842 1843 class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, 1844 vsplati8_uimm5, MSA128BOpnd>; 1845 class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, 1846 vsplati16_uimm5, MSA128HOpnd>; 1847 class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, 1848 vsplati32_uimm5, MSA128WOpnd>; 1849 class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, 1850 vsplati64_uimm5, MSA128DOpnd>; 1851 1852 class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, 1853 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1854 MSA128BOpnd>; 1855 class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, 1856 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1857 MSA128HOpnd>; 1858 class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, 1859 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1860 MSA128WOpnd>; 1861 class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, 1862 uimm1_ptr, immZExt1Ptr, GPR64Opnd, 1863 MSA128DOpnd>; 1864 1865 class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, 1866 uimm4_ptr, immZExt4Ptr, GPR32Opnd, 1867 MSA128BOpnd>; 1868 class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, 1869 uimm3_ptr, immZExt3Ptr, GPR32Opnd, 1870 MSA128HOpnd>; 1871 class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, 1872 uimm2_ptr, immZExt2Ptr, GPR32Opnd, 1873 MSA128WOpnd>; 1874 1875 class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, 1876 uimm2_ptr, immZExt2Ptr, FGR32, 1877 MSA128W>; 1878 class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, 1879 uimm1_ptr, immZExt1Ptr, FGR64, 1880 MSA128D>; 1881 1882 class CTCMSA_DESC { 1883 dag OutOperandList = (outs); 1884 dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); 1885 string AsmString = "ctcmsa\t$cd, $rs"; 1886 InstrItinClass Itinerary = NoItinerary; 1887 bit hasSideEffects = 1; 1888 bit isMoveReg = 1; 1889 } 1890 1891 class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; 1892 class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; 1893 class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; 1894 class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; 1895 1896 class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; 1897 class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; 1898 class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; 1899 class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; 1900 1901 class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, 1902 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1903 IsCommutable; 1904 class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, 1905 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1906 IsCommutable; 1907 class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, 1908 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1909 IsCommutable; 1910 1911 class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, 1912 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, 1913 IsCommutable; 1914 class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, 1915 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, 1916 IsCommutable; 1917 class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, 1918 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, 1919 IsCommutable; 1920 1921 class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, 1922 MSA128HOpnd, MSA128BOpnd, 1923 MSA128BOpnd>, IsCommutable; 1924 class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, 1925 MSA128WOpnd, MSA128HOpnd, 1926 MSA128HOpnd>, IsCommutable; 1927 class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, 1928 MSA128DOpnd, MSA128WOpnd, 1929 MSA128WOpnd>, IsCommutable; 1930 1931 class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, 1932 MSA128HOpnd, MSA128BOpnd, 1933 MSA128BOpnd>, IsCommutable; 1934 class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, 1935 MSA128WOpnd, MSA128HOpnd, 1936 MSA128HOpnd>, IsCommutable; 1937 class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, 1938 MSA128DOpnd, MSA128WOpnd, 1939 MSA128WOpnd>, IsCommutable; 1940 1941 class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, 1942 MSA128HOpnd, MSA128BOpnd, 1943 MSA128BOpnd>; 1944 class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, 1945 MSA128WOpnd, MSA128HOpnd, 1946 MSA128HOpnd>; 1947 class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, 1948 MSA128DOpnd, MSA128WOpnd, 1949 MSA128WOpnd>; 1950 1951 class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, 1952 MSA128HOpnd, MSA128BOpnd, 1953 MSA128BOpnd>; 1954 class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, 1955 MSA128WOpnd, MSA128HOpnd, 1956 MSA128HOpnd>; 1957 class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, 1958 MSA128DOpnd, MSA128WOpnd, 1959 MSA128WOpnd>; 1960 1961 class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, 1962 IsCommutable; 1963 class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, 1964 IsCommutable; 1965 1966 class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, 1967 IsCommutable; 1968 class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, 1969 IsCommutable; 1970 1971 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, 1972 IsCommutable; 1973 class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, 1974 IsCommutable; 1975 1976 class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, 1977 MSA128WOpnd>; 1978 class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, 1979 MSA128DOpnd>; 1980 1981 class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; 1982 class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; 1983 1984 class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; 1985 class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; 1986 1987 class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, 1988 IsCommutable; 1989 class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, 1990 IsCommutable; 1991 1992 class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, 1993 IsCommutable; 1994 class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, 1995 IsCommutable; 1996 1997 class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, 1998 IsCommutable; 1999 class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, 2000 IsCommutable; 2001 2002 class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, 2003 IsCommutable; 2004 class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, 2005 IsCommutable; 2006 2007 class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, 2008 IsCommutable; 2009 class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, 2010 IsCommutable; 2011 2012 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, 2013 IsCommutable; 2014 class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, 2015 IsCommutable; 2016 2017 class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, 2018 IsCommutable; 2019 class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, 2020 IsCommutable; 2021 2022 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; 2023 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; 2024 2025 class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, 2026 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2027 class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, 2028 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2029 2030 // The fexp2.df instruction multiplies the first operand by 2 to the power of 2031 // the second operand. We therefore need a pseudo-insn in order to invent the 2032 // 1.0 when we only need to match ISD::FEXP2. 2033 class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; 2034 class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; 2035 let usesCustomInserter = 1 in { 2036 class FEXP2_W_1_PSEUDO_DESC : 2037 MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), 2038 [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; 2039 class FEXP2_D_1_PSEUDO_DESC : 2040 MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), 2041 [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; 2042 } 2043 2044 class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, 2045 MSA128WOpnd, MSA128HOpnd>; 2046 class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, 2047 MSA128DOpnd, MSA128WOpnd>; 2048 2049 class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, 2050 MSA128WOpnd, MSA128HOpnd>; 2051 class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, 2052 MSA128DOpnd, MSA128WOpnd>; 2053 2054 class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; 2055 class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; 2056 2057 class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; 2058 class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; 2059 2060 class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, 2061 MSA128WOpnd, MSA128HOpnd>; 2062 class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, 2063 MSA128DOpnd, MSA128WOpnd>; 2064 2065 class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, 2066 MSA128WOpnd, MSA128HOpnd>; 2067 class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, 2068 MSA128DOpnd, MSA128WOpnd>; 2069 2070 class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, 2071 MSA128BOpnd, GPR32Opnd>; 2072 class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, 2073 MSA128HOpnd, GPR32Opnd>; 2074 class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, 2075 MSA128WOpnd, GPR32Opnd>; 2076 class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, 2077 MSA128DOpnd, GPR64Opnd>; 2078 2079 class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W, 2080 FGR32>; 2081 class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D, 2082 FGR64>; 2083 2084 class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; 2085 class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; 2086 2087 class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; 2088 class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; 2089 2090 class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; 2091 class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; 2092 2093 class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, 2094 MSA128WOpnd>; 2095 class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, 2096 MSA128DOpnd>; 2097 2098 class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; 2099 class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; 2100 2101 class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, 2102 MSA128WOpnd>; 2103 class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, 2104 MSA128DOpnd>; 2105 2106 class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>; 2107 class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>; 2108 2109 class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; 2110 class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; 2111 2112 class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; 2113 class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; 2114 2115 class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; 2116 class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; 2117 2118 class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, 2119 MSA128WOpnd>; 2120 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, 2121 MSA128DOpnd>; 2122 2123 class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; 2124 class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; 2125 2126 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; 2127 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; 2128 2129 class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; 2130 class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; 2131 2132 class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; 2133 class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; 2134 2135 class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; 2136 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; 2137 2138 class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; 2139 class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; 2140 2141 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; 2142 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; 2143 2144 class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; 2145 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; 2146 2147 class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, 2148 MSA128WOpnd>; 2149 class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, 2150 MSA128DOpnd>; 2151 2152 class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, 2153 MSA128WOpnd>; 2154 class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, 2155 MSA128DOpnd>; 2156 2157 class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, 2158 MSA128WOpnd>; 2159 class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, 2160 MSA128DOpnd>; 2161 2162 class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, 2163 MSA128WOpnd>; 2164 class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, 2165 MSA128DOpnd>; 2166 2167 class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, 2168 MSA128WOpnd>; 2169 class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, 2170 MSA128DOpnd>; 2171 2172 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, 2173 MSA128WOpnd>; 2174 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, 2175 MSA128DOpnd>; 2176 2177 class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, 2178 MSA128WOpnd>; 2179 class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, 2180 MSA128DOpnd>; 2181 2182 class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, 2183 MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; 2184 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, 2185 MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; 2186 2187 class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, 2188 MSA128WOpnd>; 2189 class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, 2190 MSA128DOpnd>; 2191 2192 class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, 2193 MSA128WOpnd>; 2194 class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, 2195 MSA128DOpnd>; 2196 2197 class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, 2198 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2199 class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, 2200 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2201 class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, 2202 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2203 2204 class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, 2205 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2206 class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, 2207 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2208 class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, 2209 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2210 2211 class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, 2212 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2213 class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, 2214 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2215 class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, 2216 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2217 2218 class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, 2219 MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; 2220 class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, 2221 MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; 2222 class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, 2223 MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; 2224 2225 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; 2226 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; 2227 class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; 2228 class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; 2229 2230 class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; 2231 class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; 2232 class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; 2233 class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; 2234 2235 class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; 2236 class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; 2237 class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; 2238 class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; 2239 2240 class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; 2241 class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; 2242 class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; 2243 class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; 2244 2245 class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4, 2246 immZExt4Ptr, MSA128BOpnd, GPR32Opnd>; 2247 class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3, 2248 immZExt3Ptr, MSA128HOpnd, GPR32Opnd>; 2249 class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2, 2250 immZExt2Ptr, MSA128WOpnd, GPR32Opnd>; 2251 class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1, 2252 immZExt1Ptr, MSA128DOpnd, GPR64Opnd>; 2253 2254 class INSERT_B_VIDX_PSEUDO_DESC : 2255 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>; 2256 class INSERT_H_VIDX_PSEUDO_DESC : 2257 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>; 2258 class INSERT_W_VIDX_PSEUDO_DESC : 2259 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>; 2260 class INSERT_D_VIDX_PSEUDO_DESC : 2261 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>; 2262 2263 class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, 2264 uimm2, immZExt2Ptr, 2265 MSA128WOpnd, FGR32Opnd>; 2266 class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, 2267 uimm1, immZExt1Ptr, 2268 MSA128DOpnd, FGR64Opnd>; 2269 2270 class INSERT_FW_VIDX_PSEUDO_DESC : 2271 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>; 2272 class INSERT_FD_VIDX_PSEUDO_DESC : 2273 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>; 2274 2275 class INSERT_B_VIDX64_PSEUDO_DESC : 2276 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>; 2277 class INSERT_H_VIDX64_PSEUDO_DESC : 2278 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>; 2279 class INSERT_W_VIDX64_PSEUDO_DESC : 2280 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>; 2281 class INSERT_D_VIDX64_PSEUDO_DESC : 2282 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>; 2283 2284 class INSERT_FW_VIDX64_PSEUDO_DESC : 2285 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>; 2286 class INSERT_FD_VIDX64_PSEUDO_DESC : 2287 MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>; 2288 2289 class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, immZExt4, 2290 MSA128BOpnd>; 2291 class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, immZExt3, 2292 MSA128HOpnd>; 2293 class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, immZExt2, 2294 MSA128WOpnd>; 2295 class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, immZExt1, 2296 MSA128DOpnd>; 2297 2298 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2299 ValueType TyNode, RegisterOperand ROWD, 2300 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2301 InstrItinClass itin = NoItinerary> { 2302 dag OutOperandList = (outs ROWD:$wd); 2303 dag InOperandList = (ins MemOpnd:$addr); 2304 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2305 list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; 2306 InstrItinClass Itinerary = itin; 2307 string DecoderMethod = "DecodeMSA128Mem"; 2308 } 2309 2310 class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>; 2311 class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, 2312 mem_simm10_lsl1, addrimm10lsl1>; 2313 class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, 2314 mem_simm10_lsl2, addrimm10lsl2>; 2315 class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, 2316 mem_simm10_lsl3, addrimm10lsl3>; 2317 2318 class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; 2319 class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; 2320 class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; 2321 class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; 2322 2323 class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, 2324 InstrItinClass itin = NoItinerary> { 2325 dag OutOperandList = (outs RORD:$rd); 2326 dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa); 2327 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); 2328 list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt, 2329 (shl RORD:$rs, 2330 immZExt2Lsa:$sa)))]; 2331 InstrItinClass Itinerary = itin; 2332 } 2333 2334 class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd, II_LSA>; 2335 class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd, II_DLSA>; 2336 2337 class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h, 2338 MSA128HOpnd>; 2339 class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w, 2340 MSA128WOpnd>; 2341 2342 class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h, 2343 MSA128HOpnd>; 2344 class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w, 2345 MSA128WOpnd>; 2346 2347 class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>; 2348 class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>; 2349 class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>; 2350 class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>; 2351 2352 class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>; 2353 class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>; 2354 class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>; 2355 class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>; 2356 2357 class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", smax, MSA128BOpnd>; 2358 class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", smax, MSA128HOpnd>; 2359 class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", smax, MSA128WOpnd>; 2360 class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", smax, MSA128DOpnd>; 2361 2362 class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", umax, MSA128BOpnd>; 2363 class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", umax, MSA128HOpnd>; 2364 class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", umax, MSA128WOpnd>; 2365 class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", umax, MSA128DOpnd>; 2366 2367 class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", smax, vsplati8_simm5, 2368 MSA128BOpnd>; 2369 class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", smax, vsplati16_simm5, 2370 MSA128HOpnd>; 2371 class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", smax, vsplati32_simm5, 2372 MSA128WOpnd>; 2373 class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", smax, vsplati64_simm5, 2374 MSA128DOpnd>; 2375 2376 class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", umax, vsplati8_uimm5, 2377 MSA128BOpnd>; 2378 class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", umax, vsplati16_uimm5, 2379 MSA128HOpnd>; 2380 class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", umax, vsplati32_uimm5, 2381 MSA128WOpnd>; 2382 class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", umax, vsplati64_uimm5, 2383 MSA128DOpnd>; 2384 2385 class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>; 2386 class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>; 2387 class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>; 2388 class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>; 2389 2390 class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", smin, MSA128BOpnd>; 2391 class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", smin, MSA128HOpnd>; 2392 class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", smin, MSA128WOpnd>; 2393 class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", smin, MSA128DOpnd>; 2394 2395 class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", umin, MSA128BOpnd>; 2396 class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", umin, MSA128HOpnd>; 2397 class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", umin, MSA128WOpnd>; 2398 class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", umin, MSA128DOpnd>; 2399 2400 class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", smin, vsplati8_simm5, 2401 MSA128BOpnd>; 2402 class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", smin, vsplati16_simm5, 2403 MSA128HOpnd>; 2404 class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", smin, vsplati32_simm5, 2405 MSA128WOpnd>; 2406 class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", smin, vsplati64_simm5, 2407 MSA128DOpnd>; 2408 2409 class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", umin, vsplati8_uimm5, 2410 MSA128BOpnd>; 2411 class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", umin, vsplati16_uimm5, 2412 MSA128HOpnd>; 2413 class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", umin, vsplati32_uimm5, 2414 MSA128WOpnd>; 2415 class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", umin, vsplati64_uimm5, 2416 MSA128DOpnd>; 2417 2418 class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>; 2419 class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>; 2420 class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>; 2421 class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>; 2422 2423 class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>; 2424 class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>; 2425 class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>; 2426 class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>; 2427 2428 class MOVE_V_DESC { 2429 dag OutOperandList = (outs MSA128BOpnd:$wd); 2430 dag InOperandList = (ins MSA128BOpnd:$ws); 2431 string AsmString = "move.v\t$wd, $ws"; 2432 list<dag> Pattern = []; 2433 InstrItinClass Itinerary = NoItinerary; 2434 bit isMoveReg = 1; 2435 } 2436 2437 class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h, 2438 MSA128HOpnd>; 2439 class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w, 2440 MSA128WOpnd>; 2441 2442 class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h, 2443 MSA128HOpnd>; 2444 class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w, 2445 MSA128WOpnd>; 2446 2447 class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>; 2448 class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>; 2449 class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>; 2450 class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>; 2451 2452 class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h, 2453 MSA128HOpnd>; 2454 class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w, 2455 MSA128WOpnd>; 2456 2457 class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h, 2458 MSA128HOpnd>; 2459 class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w, 2460 MSA128WOpnd>; 2461 2462 class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>; 2463 class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>; 2464 class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>; 2465 class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>; 2466 2467 class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>; 2468 class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>; 2469 class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>; 2470 class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>; 2471 2472 class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>; 2473 class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>; 2474 class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>; 2475 class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>; 2476 2477 class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>; 2478 class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>; 2479 class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>; 2480 class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>; 2481 2482 class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8, 2483 MSA128BOpnd>; 2484 2485 class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>; 2486 class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>; 2487 class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>; 2488 class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>; 2489 2490 class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>; 2491 2492 class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>; 2493 class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>; 2494 class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>; 2495 class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>; 2496 2497 class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>; 2498 class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>; 2499 class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>; 2500 class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>; 2501 2502 class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>; 2503 class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>; 2504 class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>; 2505 class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>; 2506 2507 class SAT_S_B_DESC : MSA_BIT_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b, uimm3, 2508 immZExt3, MSA128BOpnd>; 2509 class SAT_S_H_DESC : MSA_BIT_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h, uimm4, 2510 immZExt4, MSA128HOpnd>; 2511 class SAT_S_W_DESC : MSA_BIT_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w, uimm5, 2512 immZExt5, MSA128WOpnd>; 2513 class SAT_S_D_DESC : MSA_BIT_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d, uimm6, 2514 immZExt6, MSA128DOpnd>; 2515 2516 class SAT_U_B_DESC : MSA_BIT_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b, uimm3, 2517 immZExt3, MSA128BOpnd>; 2518 class SAT_U_H_DESC : MSA_BIT_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h, uimm4, 2519 immZExt4, MSA128HOpnd>; 2520 class SAT_U_W_DESC : MSA_BIT_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w, uimm5, 2521 immZExt5, MSA128WOpnd>; 2522 class SAT_U_D_DESC : MSA_BIT_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d, uimm6, 2523 immZExt6, MSA128DOpnd>; 2524 2525 class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>; 2526 class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>; 2527 class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>; 2528 2529 class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>; 2530 class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>; 2531 class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>; 2532 class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>; 2533 2534 class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b, 2535 MSA128BOpnd, MSA128BOpnd, uimm4, 2536 immZExt4>; 2537 class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h, 2538 MSA128HOpnd, MSA128HOpnd, uimm3, 2539 immZExt3>; 2540 class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w, 2541 MSA128WOpnd, MSA128WOpnd, uimm2, 2542 immZExt2>; 2543 class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d, 2544 MSA128DOpnd, MSA128DOpnd, uimm1, 2545 immZExt1>; 2546 2547 class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>; 2548 class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>; 2549 class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>; 2550 class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>; 2551 2552 class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3, 2553 MSA128BOpnd>; 2554 class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4, 2555 MSA128HOpnd>; 2556 class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5, 2557 MSA128WOpnd>; 2558 class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6, 2559 MSA128DOpnd>; 2560 2561 class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt, 2562 MSA128BOpnd>; 2563 class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt, 2564 MSA128HOpnd>; 2565 class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt, 2566 MSA128WOpnd>; 2567 class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt, 2568 MSA128DOpnd>; 2569 2570 class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4, 2571 MSA128BOpnd>; 2572 class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3, 2573 MSA128HOpnd>; 2574 class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2, 2575 MSA128WOpnd>; 2576 class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1, 2577 MSA128DOpnd>; 2578 2579 class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>; 2580 class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>; 2581 class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>; 2582 class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>; 2583 2584 class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3, 2585 MSA128BOpnd>; 2586 class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4, 2587 MSA128HOpnd>; 2588 class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5, 2589 MSA128WOpnd>; 2590 class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6, 2591 MSA128DOpnd>; 2592 2593 class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>; 2594 class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>; 2595 class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>; 2596 class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>; 2597 2598 class SRARI_B_DESC : MSA_BIT_X_DESC_BASE<"srari.b", int_mips_srari_b, uimm3, 2599 immZExt3, MSA128BOpnd>; 2600 class SRARI_H_DESC : MSA_BIT_X_DESC_BASE<"srari.h", int_mips_srari_h, uimm4, 2601 immZExt4, MSA128HOpnd>; 2602 class SRARI_W_DESC : MSA_BIT_X_DESC_BASE<"srari.w", int_mips_srari_w, uimm5, 2603 immZExt5, MSA128WOpnd>; 2604 class SRARI_D_DESC : MSA_BIT_X_DESC_BASE<"srari.d", int_mips_srari_d, uimm6, 2605 immZExt6, MSA128DOpnd>; 2606 2607 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>; 2608 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>; 2609 class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>; 2610 class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>; 2611 2612 class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3, 2613 MSA128BOpnd>; 2614 class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4, 2615 MSA128HOpnd>; 2616 class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5, 2617 MSA128WOpnd>; 2618 class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6, 2619 MSA128DOpnd>; 2620 2621 class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>; 2622 class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>; 2623 class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>; 2624 class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>; 2625 2626 class SRLRI_B_DESC : MSA_BIT_X_DESC_BASE<"srlri.b", int_mips_srlri_b, uimm3, 2627 immZExt3, MSA128BOpnd>; 2628 class SRLRI_H_DESC : MSA_BIT_X_DESC_BASE<"srlri.h", int_mips_srlri_h, uimm4, 2629 immZExt4, MSA128HOpnd>; 2630 class SRLRI_W_DESC : MSA_BIT_X_DESC_BASE<"srlri.w", int_mips_srlri_w, uimm5, 2631 immZExt5, MSA128WOpnd>; 2632 class SRLRI_D_DESC : MSA_BIT_X_DESC_BASE<"srlri.d", int_mips_srlri_d, uimm6, 2633 immZExt6, MSA128DOpnd>; 2634 2635 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, 2636 ValueType TyNode, RegisterOperand ROWD, 2637 Operand MemOpnd, ComplexPattern Addr = addrimm10, 2638 InstrItinClass itin = NoItinerary> { 2639 dag OutOperandList = (outs); 2640 dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr); 2641 string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); 2642 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)]; 2643 InstrItinClass Itinerary = itin; 2644 string DecoderMethod = "DecodeMSA128Mem"; 2645 } 2646 2647 class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>; 2648 class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, 2649 mem_simm10_lsl1, addrimm10lsl1>; 2650 class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, 2651 mem_simm10_lsl2, addrimm10lsl2>; 2652 class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, 2653 mem_simm10_lsl3, addrimm10lsl3>; 2654 2655 class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, 2656 MSA128BOpnd>; 2657 class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h, 2658 MSA128HOpnd>; 2659 class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w, 2660 MSA128WOpnd>; 2661 class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d, 2662 MSA128DOpnd>; 2663 2664 class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b, 2665 MSA128BOpnd>; 2666 class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h, 2667 MSA128HOpnd>; 2668 class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w, 2669 MSA128WOpnd>; 2670 class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d, 2671 MSA128DOpnd>; 2672 2673 class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b, 2674 MSA128BOpnd>; 2675 class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h, 2676 MSA128HOpnd>; 2677 class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w, 2678 MSA128WOpnd>; 2679 class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d, 2680 MSA128DOpnd>; 2681 2682 class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b, 2683 MSA128BOpnd>; 2684 class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h, 2685 MSA128HOpnd>; 2686 class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w, 2687 MSA128WOpnd>; 2688 class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d, 2689 MSA128DOpnd>; 2690 2691 class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>; 2692 class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>; 2693 class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>; 2694 class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>; 2695 2696 class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5, 2697 MSA128BOpnd>; 2698 class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5, 2699 MSA128HOpnd>; 2700 class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5, 2701 MSA128WOpnd>; 2702 class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5, 2703 MSA128DOpnd>; 2704 2705 class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>; 2706 class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>; 2707 class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>; 2708 class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>; 2709 2710 class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>; 2711 class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>; 2712 class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>; 2713 class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>; 2714 2715 class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8, 2716 MSA128BOpnd>; 2717 2718 // Instruction defs. 2719 def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC; 2720 def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC; 2721 def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC; 2722 def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC; 2723 2724 def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC; 2725 def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC; 2726 def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC; 2727 def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC; 2728 2729 def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC; 2730 def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC; 2731 def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC; 2732 def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC; 2733 2734 def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC; 2735 def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC; 2736 def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC; 2737 def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC; 2738 2739 def ADDV_B : ADDV_B_ENC, ADDV_B_DESC; 2740 def ADDV_H : ADDV_H_ENC, ADDV_H_DESC; 2741 def ADDV_W : ADDV_W_ENC, ADDV_W_DESC; 2742 def ADDV_D : ADDV_D_ENC, ADDV_D_DESC; 2743 2744 def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC; 2745 def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC; 2746 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC; 2747 def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC; 2748 2749 def AND_V : AND_V_ENC, AND_V_DESC; 2750 def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC, 2751 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2752 MSA128BOpnd:$ws, 2753 MSA128BOpnd:$wt)>; 2754 def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC, 2755 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2756 MSA128BOpnd:$ws, 2757 MSA128BOpnd:$wt)>; 2758 def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC, 2759 PseudoInstExpansion<(AND_V MSA128BOpnd:$wd, 2760 MSA128BOpnd:$ws, 2761 MSA128BOpnd:$wt)>; 2762 2763 def ANDI_B : ANDI_B_ENC, ANDI_B_DESC; 2764 2765 def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC; 2766 def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC; 2767 def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC; 2768 def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC; 2769 2770 def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC; 2771 def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC; 2772 def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC; 2773 def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC; 2774 2775 def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC; 2776 def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC; 2777 def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC; 2778 def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC; 2779 2780 def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC; 2781 def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC; 2782 def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC; 2783 def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC; 2784 2785 def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC; 2786 def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC; 2787 def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC; 2788 def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC; 2789 2790 def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC; 2791 def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC; 2792 def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC; 2793 def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC; 2794 2795 def BCLR_B : BCLR_B_ENC, BCLR_B_DESC; 2796 def BCLR_H : BCLR_H_ENC, BCLR_H_DESC; 2797 def BCLR_W : BCLR_W_ENC, BCLR_W_DESC; 2798 def BCLR_D : BCLR_D_ENC, BCLR_D_DESC; 2799 2800 def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC; 2801 def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC; 2802 def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC; 2803 def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC; 2804 2805 def BINSL_B : BINSL_B_ENC, BINSL_B_DESC; 2806 def BINSL_H : BINSL_H_ENC, BINSL_H_DESC; 2807 def BINSL_W : BINSL_W_ENC, BINSL_W_DESC; 2808 def BINSL_D : BINSL_D_ENC, BINSL_D_DESC; 2809 2810 def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC; 2811 def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC; 2812 def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC; 2813 def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC; 2814 2815 def BINSR_B : BINSR_B_ENC, BINSR_B_DESC; 2816 def BINSR_H : BINSR_H_ENC, BINSR_H_DESC; 2817 def BINSR_W : BINSR_W_ENC, BINSR_W_DESC; 2818 def BINSR_D : BINSR_D_ENC, BINSR_D_DESC; 2819 2820 def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC; 2821 def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC; 2822 def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC; 2823 def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC; 2824 2825 def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC; 2826 2827 def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC; 2828 2829 def BMZ_V : BMZ_V_ENC, BMZ_V_DESC; 2830 2831 def BMZI_B : BMZI_B_ENC, BMZI_B_DESC; 2832 2833 def BNEG_B : BNEG_B_ENC, BNEG_B_DESC; 2834 def BNEG_H : BNEG_H_ENC, BNEG_H_DESC; 2835 def BNEG_W : BNEG_W_ENC, BNEG_W_DESC; 2836 def BNEG_D : BNEG_D_ENC, BNEG_D_DESC; 2837 2838 def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC; 2839 def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC; 2840 def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC; 2841 def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC; 2842 2843 def BNZ_B : BNZ_B_ENC, BNZ_B_DESC; 2844 def BNZ_H : BNZ_H_ENC, BNZ_H_DESC; 2845 def BNZ_W : BNZ_W_ENC, BNZ_W_DESC; 2846 def BNZ_D : BNZ_D_ENC, BNZ_D_DESC; 2847 2848 def BNZ_V : BNZ_V_ENC, BNZ_V_DESC; 2849 2850 def BSEL_V : BSEL_V_ENC, BSEL_V_DESC; 2851 2852 class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> : 2853 MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt), 2854 [(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>, 2855 // Note that vselect and BSEL_V treat the condition operand the opposite way 2856 // from each other. 2857 // (vselect cond, if_set, if_clear) 2858 // (BSEL_V cond, if_clear, if_set) 2859 PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in, 2860 MSA128BOpnd:$ws, MSA128BOpnd:$wt)> { 2861 let Constraints = "$wd_in = $wd"; 2862 } 2863 2864 def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>; 2865 def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>; 2866 def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>; 2867 def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>; 2868 def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>; 2869 2870 def BSELI_B : BSELI_B_ENC, BSELI_B_DESC; 2871 2872 def BSET_B : BSET_B_ENC, BSET_B_DESC; 2873 def BSET_H : BSET_H_ENC, BSET_H_DESC; 2874 def BSET_W : BSET_W_ENC, BSET_W_DESC; 2875 def BSET_D : BSET_D_ENC, BSET_D_DESC; 2876 2877 def BSETI_B : BSETI_B_ENC, BSETI_B_DESC; 2878 def BSETI_H : BSETI_H_ENC, BSETI_H_DESC; 2879 def BSETI_W : BSETI_W_ENC, BSETI_W_DESC; 2880 def BSETI_D : BSETI_D_ENC, BSETI_D_DESC; 2881 2882 def BZ_B : BZ_B_ENC, BZ_B_DESC; 2883 def BZ_H : BZ_H_ENC, BZ_H_DESC; 2884 def BZ_W : BZ_W_ENC, BZ_W_DESC; 2885 def BZ_D : BZ_D_ENC, BZ_D_DESC; 2886 2887 def BZ_V : BZ_V_ENC, BZ_V_DESC; 2888 2889 def CEQ_B : CEQ_B_ENC, CEQ_B_DESC; 2890 def CEQ_H : CEQ_H_ENC, CEQ_H_DESC; 2891 def CEQ_W : CEQ_W_ENC, CEQ_W_DESC; 2892 def CEQ_D : CEQ_D_ENC, CEQ_D_DESC; 2893 2894 def CEQI_B : CEQI_B_ENC, CEQI_B_DESC; 2895 def CEQI_H : CEQI_H_ENC, CEQI_H_DESC; 2896 def CEQI_W : CEQI_W_ENC, CEQI_W_DESC; 2897 def CEQI_D : CEQI_D_ENC, CEQI_D_DESC; 2898 2899 def CFCMSA : CFCMSA_ENC, CFCMSA_DESC; 2900 2901 def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC; 2902 def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC; 2903 def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC; 2904 def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC; 2905 2906 def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC; 2907 def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC; 2908 def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC; 2909 def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC; 2910 2911 def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC; 2912 def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC; 2913 def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC; 2914 def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC; 2915 2916 def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC; 2917 def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC; 2918 def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC; 2919 def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC; 2920 2921 def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC; 2922 def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC; 2923 def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC; 2924 def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC; 2925 2926 def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC; 2927 def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC; 2928 def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC; 2929 def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC; 2930 2931 def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC; 2932 def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC; 2933 def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC; 2934 def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC; 2935 2936 def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC; 2937 def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC; 2938 def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC; 2939 def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC; 2940 2941 def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC; 2942 def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC; 2943 def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC; 2944 def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC, ASE_MSA64; 2945 2946 def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC; 2947 def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC; 2948 def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC, ASE_MSA64; 2949 2950 def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC; 2951 def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC; 2952 2953 def CTCMSA : CTCMSA_ENC, CTCMSA_DESC; 2954 2955 def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC; 2956 def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC; 2957 def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC; 2958 def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC; 2959 2960 def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC; 2961 def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC; 2962 def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC; 2963 def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC; 2964 2965 def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC; 2966 def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC; 2967 def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC; 2968 2969 def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC; 2970 def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC; 2971 def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC; 2972 2973 def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC; 2974 def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC; 2975 def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC; 2976 2977 def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC; 2978 def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC; 2979 def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC; 2980 2981 def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC; 2982 def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC; 2983 def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC; 2984 2985 def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC; 2986 def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC; 2987 def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC; 2988 2989 def FADD_W : FADD_W_ENC, FADD_W_DESC; 2990 def FADD_D : FADD_D_ENC, FADD_D_DESC; 2991 2992 def FCAF_W : FCAF_W_ENC, FCAF_W_DESC; 2993 def FCAF_D : FCAF_D_ENC, FCAF_D_DESC; 2994 2995 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC; 2996 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC; 2997 2998 def FCLE_W : FCLE_W_ENC, FCLE_W_DESC; 2999 def FCLE_D : FCLE_D_ENC, FCLE_D_DESC; 3000 3001 def FCLT_W : FCLT_W_ENC, FCLT_W_DESC; 3002 def FCLT_D : FCLT_D_ENC, FCLT_D_DESC; 3003 3004 def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC; 3005 def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC; 3006 3007 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC; 3008 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC; 3009 3010 def FCOR_W : FCOR_W_ENC, FCOR_W_DESC; 3011 def FCOR_D : FCOR_D_ENC, FCOR_D_DESC; 3012 3013 def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC; 3014 def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC; 3015 3016 def FCULE_W : FCULE_W_ENC, FCULE_W_DESC; 3017 def FCULE_D : FCULE_D_ENC, FCULE_D_DESC; 3018 3019 def FCULT_W : FCULT_W_ENC, FCULT_W_DESC; 3020 def FCULT_D : FCULT_D_ENC, FCULT_D_DESC; 3021 3022 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC; 3023 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC; 3024 3025 def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC; 3026 def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC; 3027 3028 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC; 3029 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC; 3030 3031 def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC; 3032 def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; 3033 3034 def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; 3035 def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; 3036 def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; 3037 def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; 3038 3039 def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; 3040 def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; 3041 3042 def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC; 3043 def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC; 3044 3045 def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC; 3046 def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC; 3047 3048 def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC; 3049 def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC; 3050 3051 def FFQL_W : FFQL_W_ENC, FFQL_W_DESC; 3052 def FFQL_D : FFQL_D_ENC, FFQL_D_DESC; 3053 3054 def FFQR_W : FFQR_W_ENC, FFQR_W_DESC; 3055 def FFQR_D : FFQR_D_ENC, FFQR_D_DESC; 3056 3057 def FILL_B : FILL_B_ENC, FILL_B_DESC; 3058 def FILL_H : FILL_H_ENC, FILL_H_DESC; 3059 def FILL_W : FILL_W_ENC, FILL_W_DESC; 3060 def FILL_D : FILL_D_ENC, FILL_D_DESC, ASE_MSA64; 3061 def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC; 3062 def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC; 3063 3064 def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC; 3065 def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC; 3066 3067 def FMADD_W : FMADD_W_ENC, FMADD_W_DESC; 3068 def FMADD_D : FMADD_D_ENC, FMADD_D_DESC; 3069 3070 def FMAX_W : FMAX_W_ENC, FMAX_W_DESC; 3071 def FMAX_D : FMAX_D_ENC, FMAX_D_DESC; 3072 3073 def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC; 3074 def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC; 3075 3076 def FMIN_W : FMIN_W_ENC, FMIN_W_DESC; 3077 def FMIN_D : FMIN_D_ENC, FMIN_D_DESC; 3078 3079 def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC; 3080 def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC; 3081 3082 def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC; 3083 def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC; 3084 3085 def FMUL_W : FMUL_W_ENC, FMUL_W_DESC; 3086 def FMUL_D : FMUL_D_ENC, FMUL_D_DESC; 3087 3088 def FRINT_W : FRINT_W_ENC, FRINT_W_DESC; 3089 def FRINT_D : FRINT_D_ENC, FRINT_D_DESC; 3090 3091 def FRCP_W : FRCP_W_ENC, FRCP_W_DESC; 3092 def FRCP_D : FRCP_D_ENC, FRCP_D_DESC; 3093 3094 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC; 3095 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC; 3096 3097 def FSAF_W : FSAF_W_ENC, FSAF_W_DESC; 3098 def FSAF_D : FSAF_D_ENC, FSAF_D_DESC; 3099 3100 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC; 3101 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC; 3102 3103 def FSLE_W : FSLE_W_ENC, FSLE_W_DESC; 3104 def FSLE_D : FSLE_D_ENC, FSLE_D_DESC; 3105 3106 def FSLT_W : FSLT_W_ENC, FSLT_W_DESC; 3107 def FSLT_D : FSLT_D_ENC, FSLT_D_DESC; 3108 3109 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC; 3110 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC; 3111 3112 def FSOR_W : FSOR_W_ENC, FSOR_W_DESC; 3113 def FSOR_D : FSOR_D_ENC, FSOR_D_DESC; 3114 3115 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC; 3116 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC; 3117 3118 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC; 3119 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC; 3120 3121 def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC; 3122 def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC; 3123 3124 def FSULE_W : FSULE_W_ENC, FSULE_W_DESC; 3125 def FSULE_D : FSULE_D_ENC, FSULE_D_DESC; 3126 3127 def FSULT_W : FSULT_W_ENC, FSULT_W_DESC; 3128 def FSULT_D : FSULT_D_ENC, FSULT_D_DESC; 3129 3130 def FSUN_W : FSUN_W_ENC, FSUN_W_DESC; 3131 def FSUN_D : FSUN_D_ENC, FSUN_D_DESC; 3132 3133 def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC; 3134 def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC; 3135 3136 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC; 3137 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC; 3138 3139 def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC; 3140 def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC; 3141 3142 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC; 3143 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC; 3144 3145 def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC; 3146 def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC; 3147 3148 def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC; 3149 def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC; 3150 3151 def : MipsPat<(fsub MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), 3152 (FMSUB_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, 3153 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3154 def : MipsPat<(fsub MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), 3155 (FMSUB_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, 3156 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3157 3158 def : MipsPat<(fadd MSA128WOpnd:$wd, (fmul MSA128WOpnd:$ws, MSA128WOpnd:$wt)), 3159 (FMADD_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, MSA128WOpnd:$wt)>, 3160 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3161 def : MipsPat<(fadd MSA128DOpnd:$wd, (fmul MSA128DOpnd:$ws, MSA128DOpnd:$wt)), 3162 (FMADD_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, MSA128DOpnd:$wt)>, 3163 ISA_MIPS1, ASE_MSA, FPOP_FUSION_FAST; 3164 3165 def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC; 3166 def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC; 3167 def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC; 3168 3169 def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC; 3170 def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC; 3171 def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC; 3172 3173 def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC; 3174 def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC; 3175 def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC; 3176 3177 def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC; 3178 def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC; 3179 def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC; 3180 3181 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC; 3182 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC; 3183 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC; 3184 def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC; 3185 3186 def ILVL_B : ILVL_B_ENC, ILVL_B_DESC; 3187 def ILVL_H : ILVL_H_ENC, ILVL_H_DESC; 3188 def ILVL_W : ILVL_W_ENC, ILVL_W_DESC; 3189 def ILVL_D : ILVL_D_ENC, ILVL_D_DESC; 3190 3191 def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC; 3192 def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC; 3193 def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC; 3194 def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC; 3195 3196 def ILVR_B : ILVR_B_ENC, ILVR_B_DESC; 3197 def ILVR_H : ILVR_H_ENC, ILVR_H_DESC; 3198 def ILVR_W : ILVR_W_ENC, ILVR_W_DESC; 3199 def ILVR_D : ILVR_D_ENC, ILVR_D_DESC; 3200 3201 def INSERT_B : INSERT_B_ENC, INSERT_B_DESC; 3202 def INSERT_H : INSERT_H_ENC, INSERT_H_DESC; 3203 def INSERT_W : INSERT_W_ENC, INSERT_W_DESC; 3204 def INSERT_D : INSERT_D_ENC, INSERT_D_DESC, ASE_MSA64; 3205 3206 // INSERT_FW_PSEUDO defined after INSVE_W 3207 // INSERT_FD_PSEUDO defined after INSVE_D 3208 3209 // There is a fourth operand that is not present in the encoding. Use a 3210 // custom decoder to get a chance to add it. 3211 let DecoderMethod = "DecodeINSVE_DF" in { 3212 def INSVE_B : INSVE_B_ENC, INSVE_B_DESC; 3213 def INSVE_H : INSVE_H_ENC, INSVE_H_DESC; 3214 def INSVE_W : INSVE_W_ENC, INSVE_W_DESC; 3215 def INSVE_D : INSVE_D_ENC, INSVE_D_DESC; 3216 } 3217 3218 def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC; 3219 def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC; 3220 3221 def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC; 3222 def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC; 3223 def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC; 3224 def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC; 3225 def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC; 3226 def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC; 3227 3228 def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC; 3229 def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC; 3230 def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC; 3231 def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC; 3232 def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC; 3233 def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC; 3234 3235 def LD_B: LD_B_ENC, LD_B_DESC; 3236 def LD_H: LD_H_ENC, LD_H_DESC; 3237 def LD_W: LD_W_ENC, LD_W_DESC; 3238 def LD_D: LD_D_ENC, LD_D_DESC; 3239 3240 def LDI_B : LDI_B_ENC, LDI_B_DESC; 3241 def LDI_H : LDI_H_ENC, LDI_H_DESC; 3242 def LDI_W : LDI_W_ENC, LDI_W_DESC; 3243 def LDI_D : LDI_D_ENC, LDI_D_DESC; 3244 3245 def LSA : LSA_ENC, LSA_DESC; 3246 def DLSA : DLSA_ENC, DLSA_DESC, ASE_MSA64; 3247 3248 def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC; 3249 def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC; 3250 3251 def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC; 3252 def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC; 3253 3254 def MADDV_B : MADDV_B_ENC, MADDV_B_DESC; 3255 def MADDV_H : MADDV_H_ENC, MADDV_H_DESC; 3256 def MADDV_W : MADDV_W_ENC, MADDV_W_DESC; 3257 def MADDV_D : MADDV_D_ENC, MADDV_D_DESC; 3258 3259 def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC; 3260 def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC; 3261 def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC; 3262 def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC; 3263 3264 def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC; 3265 def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC; 3266 def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC; 3267 def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC; 3268 3269 def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC; 3270 def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC; 3271 def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC; 3272 def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC; 3273 3274 def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC; 3275 def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC; 3276 def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC; 3277 def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC; 3278 3279 def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC; 3280 def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC; 3281 def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC; 3282 def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC; 3283 3284 def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC; 3285 def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC; 3286 def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC; 3287 def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC; 3288 3289 def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC; 3290 def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC; 3291 def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC; 3292 def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC; 3293 3294 def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC; 3295 def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC; 3296 def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC; 3297 def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC; 3298 3299 def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC; 3300 def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC; 3301 def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC; 3302 def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC; 3303 3304 def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC; 3305 def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC; 3306 def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC; 3307 def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC; 3308 3309 def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC; 3310 def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC; 3311 def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC; 3312 def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC; 3313 3314 def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC; 3315 def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC; 3316 def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC; 3317 def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC; 3318 3319 def MOVE_V : MOVE_V_ENC, MOVE_V_DESC; 3320 3321 def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC; 3322 def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC; 3323 3324 def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC; 3325 def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC; 3326 3327 def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC; 3328 def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC; 3329 def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC; 3330 def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC; 3331 3332 def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC; 3333 def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC; 3334 3335 def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC; 3336 def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC; 3337 3338 def MULV_B : MULV_B_ENC, MULV_B_DESC; 3339 def MULV_H : MULV_H_ENC, MULV_H_DESC; 3340 def MULV_W : MULV_W_ENC, MULV_W_DESC; 3341 def MULV_D : MULV_D_ENC, MULV_D_DESC; 3342 3343 def NLOC_B : NLOC_B_ENC, NLOC_B_DESC; 3344 def NLOC_H : NLOC_H_ENC, NLOC_H_DESC; 3345 def NLOC_W : NLOC_W_ENC, NLOC_W_DESC; 3346 def NLOC_D : NLOC_D_ENC, NLOC_D_DESC; 3347 3348 def NLZC_B : NLZC_B_ENC, NLZC_B_DESC; 3349 def NLZC_H : NLZC_H_ENC, NLZC_H_DESC; 3350 def NLZC_W : NLZC_W_ENC, NLZC_W_DESC; 3351 def NLZC_D : NLZC_D_ENC, NLZC_D_DESC; 3352 3353 def NOR_V : NOR_V_ENC, NOR_V_DESC; 3354 def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC, 3355 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3356 MSA128BOpnd:$ws, 3357 MSA128BOpnd:$wt)>; 3358 def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC, 3359 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3360 MSA128BOpnd:$ws, 3361 MSA128BOpnd:$wt)>; 3362 def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC, 3363 PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd, 3364 MSA128BOpnd:$ws, 3365 MSA128BOpnd:$wt)>; 3366 3367 def NORI_B : NORI_B_ENC, NORI_B_DESC; 3368 3369 def OR_V : OR_V_ENC, OR_V_DESC; 3370 def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC, 3371 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3372 MSA128BOpnd:$ws, 3373 MSA128BOpnd:$wt)>; 3374 def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC, 3375 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3376 MSA128BOpnd:$ws, 3377 MSA128BOpnd:$wt)>; 3378 def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC, 3379 PseudoInstExpansion<(OR_V MSA128BOpnd:$wd, 3380 MSA128BOpnd:$ws, 3381 MSA128BOpnd:$wt)>; 3382 3383 def ORI_B : ORI_B_ENC, ORI_B_DESC; 3384 3385 def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC; 3386 def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC; 3387 def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC; 3388 def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC; 3389 3390 def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC; 3391 def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC; 3392 def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC; 3393 def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC; 3394 3395 def PCNT_B : PCNT_B_ENC, PCNT_B_DESC; 3396 def PCNT_H : PCNT_H_ENC, PCNT_H_DESC; 3397 def PCNT_W : PCNT_W_ENC, PCNT_W_DESC; 3398 def PCNT_D : PCNT_D_ENC, PCNT_D_DESC; 3399 3400 def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC; 3401 def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC; 3402 def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC; 3403 def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC; 3404 3405 def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC; 3406 def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC; 3407 def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC; 3408 def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC; 3409 3410 def SHF_B : SHF_B_ENC, SHF_B_DESC; 3411 def SHF_H : SHF_H_ENC, SHF_H_DESC; 3412 def SHF_W : SHF_W_ENC, SHF_W_DESC; 3413 3414 def SLD_B : SLD_B_ENC, SLD_B_DESC; 3415 def SLD_H : SLD_H_ENC, SLD_H_DESC; 3416 def SLD_W : SLD_W_ENC, SLD_W_DESC; 3417 def SLD_D : SLD_D_ENC, SLD_D_DESC; 3418 3419 def SLDI_B : SLDI_B_ENC, SLDI_B_DESC; 3420 def SLDI_H : SLDI_H_ENC, SLDI_H_DESC; 3421 def SLDI_W : SLDI_W_ENC, SLDI_W_DESC; 3422 def SLDI_D : SLDI_D_ENC, SLDI_D_DESC; 3423 3424 def SLL_B : SLL_B_ENC, SLL_B_DESC; 3425 def SLL_H : SLL_H_ENC, SLL_H_DESC; 3426 def SLL_W : SLL_W_ENC, SLL_W_DESC; 3427 def SLL_D : SLL_D_ENC, SLL_D_DESC; 3428 3429 def SLLI_B : SLLI_B_ENC, SLLI_B_DESC; 3430 def SLLI_H : SLLI_H_ENC, SLLI_H_DESC; 3431 def SLLI_W : SLLI_W_ENC, SLLI_W_DESC; 3432 def SLLI_D : SLLI_D_ENC, SLLI_D_DESC; 3433 3434 def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC; 3435 def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC; 3436 def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC; 3437 def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC; 3438 3439 def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC; 3440 def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC; 3441 def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC; 3442 def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC; 3443 3444 def SRA_B : SRA_B_ENC, SRA_B_DESC; 3445 def SRA_H : SRA_H_ENC, SRA_H_DESC; 3446 def SRA_W : SRA_W_ENC, SRA_W_DESC; 3447 def SRA_D : SRA_D_ENC, SRA_D_DESC; 3448 3449 def SRAI_B : SRAI_B_ENC, SRAI_B_DESC; 3450 def SRAI_H : SRAI_H_ENC, SRAI_H_DESC; 3451 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC; 3452 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC; 3453 3454 def SRAR_B : SRAR_B_ENC, SRAR_B_DESC; 3455 def SRAR_H : SRAR_H_ENC, SRAR_H_DESC; 3456 def SRAR_W : SRAR_W_ENC, SRAR_W_DESC; 3457 def SRAR_D : SRAR_D_ENC, SRAR_D_DESC; 3458 3459 def SRARI_B : SRARI_B_ENC, SRARI_B_DESC; 3460 def SRARI_H : SRARI_H_ENC, SRARI_H_DESC; 3461 def SRARI_W : SRARI_W_ENC, SRARI_W_DESC; 3462 def SRARI_D : SRARI_D_ENC, SRARI_D_DESC; 3463 3464 def SRL_B : SRL_B_ENC, SRL_B_DESC; 3465 def SRL_H : SRL_H_ENC, SRL_H_DESC; 3466 def SRL_W : SRL_W_ENC, SRL_W_DESC; 3467 def SRL_D : SRL_D_ENC, SRL_D_DESC; 3468 3469 def SRLI_B : SRLI_B_ENC, SRLI_B_DESC; 3470 def SRLI_H : SRLI_H_ENC, SRLI_H_DESC; 3471 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC; 3472 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC; 3473 3474 def SRLR_B : SRLR_B_ENC, SRLR_B_DESC; 3475 def SRLR_H : SRLR_H_ENC, SRLR_H_DESC; 3476 def SRLR_W : SRLR_W_ENC, SRLR_W_DESC; 3477 def SRLR_D : SRLR_D_ENC, SRLR_D_DESC; 3478 3479 def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC; 3480 def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC; 3481 def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC; 3482 def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC; 3483 3484 def ST_B: ST_B_ENC, ST_B_DESC; 3485 def ST_H: ST_H_ENC, ST_H_DESC; 3486 def ST_W: ST_W_ENC, ST_W_DESC; 3487 def ST_D: ST_D_ENC, ST_D_DESC; 3488 3489 def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC; 3490 def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC; 3491 def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC; 3492 def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC; 3493 3494 def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC; 3495 def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC; 3496 def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC; 3497 def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC; 3498 3499 def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC; 3500 def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC; 3501 def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC; 3502 def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC; 3503 3504 def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC; 3505 def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC; 3506 def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC; 3507 def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC; 3508 3509 def SUBV_B : SUBV_B_ENC, SUBV_B_DESC; 3510 def SUBV_H : SUBV_H_ENC, SUBV_H_DESC; 3511 def SUBV_W : SUBV_W_ENC, SUBV_W_DESC; 3512 def SUBV_D : SUBV_D_ENC, SUBV_D_DESC; 3513 3514 def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC; 3515 def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC; 3516 def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC; 3517 def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC; 3518 3519 def VSHF_B : VSHF_B_ENC, VSHF_B_DESC; 3520 def VSHF_H : VSHF_H_ENC, VSHF_H_DESC; 3521 def VSHF_W : VSHF_W_ENC, VSHF_W_DESC; 3522 def VSHF_D : VSHF_D_ENC, VSHF_D_DESC; 3523 3524 def XOR_V : XOR_V_ENC, XOR_V_DESC; 3525 def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC, 3526 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3527 MSA128BOpnd:$ws, 3528 MSA128BOpnd:$wt)>; 3529 def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC, 3530 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3531 MSA128BOpnd:$ws, 3532 MSA128BOpnd:$wt)>; 3533 def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC, 3534 PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd, 3535 MSA128BOpnd:$ws, 3536 MSA128BOpnd:$wt)>; 3537 3538 def XORI_B : XORI_B_ENC, XORI_B_DESC; 3539 3540 // Patterns. 3541 class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : 3542 Pat<pattern, result>, Requires<pred>; 3543 3544 def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), 3545 (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; 3546 3547 def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>; 3548 def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>; 3549 def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>; 3550 3551 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr), 3552 (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>; 3553 def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr), 3554 (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>; 3555 def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr), 3556 (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>; 3557 3558 class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, 3559 RegisterOperand ROWS = ROWD, 3560 InstrItinClass itin = NoItinerary> : 3561 MSAPseudo<(outs ROWD:$wd), 3562 (ins ROWS:$ws), 3563 [(set ROWD:$wd, (fabs ROWS:$ws))]> { 3564 InstrItinClass Itinerary = itin; 3565 } 3566 def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>, 3567 PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws, 3568 MSA128WOpnd:$ws)>; 3569 def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>, 3570 PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws, 3571 MSA128DOpnd:$ws)>; 3572 3573 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT, 3574 RegisterClass DstRC, list<Predicate> preds = [HasMSA]> : 3575 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3576 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>; 3577 3578 // These are endian-independent because the element size doesnt change 3579 def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3580 def : MSABitconvertPat<v4i32, v4f32, MSA128W>; 3581 def : MSABitconvertPat<v2i64, v2f64, MSA128D>; 3582 def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3583 def : MSABitconvertPat<v4f32, v4i32, MSA128W>; 3584 def : MSABitconvertPat<v2f64, v2i64, MSA128D>; 3585 3586 // Little endian bitcasts are always no-ops 3587 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3588 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3589 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3590 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3591 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3592 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3593 3594 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3595 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3596 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3597 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; 3598 def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>; 3599 3600 def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>; 3601 def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>; 3602 def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>; 3603 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3604 def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>; 3605 3606 def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>; 3607 def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>; 3608 def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>; 3609 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3610 def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>; 3611 3612 def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>; 3613 def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>; 3614 def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>; 3615 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3616 def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>; 3617 3618 def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>; 3619 def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>; 3620 def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>; 3621 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3622 def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>; 3623 3624 // Big endian bitcasts expand to shuffle instructions. 3625 // This is because bitcast is defined to be a store/load sequence and the 3626 // vector store/load instructions are mixed-endian with respect to the vector 3627 // as a whole (little endian with respect to element order, but big endian 3628 // elements). 3629 3630 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT, 3631 RegisterClass DstRC, MSAInst Insn, 3632 RegisterClass ViaRC> : 3633 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3634 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27), 3635 DstRC), 3636 [HasMSA, IsBE]>; 3637 3638 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT, 3639 RegisterClass DstRC, MSAInst Insn, 3640 RegisterClass ViaRC> : 3641 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3642 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177), 3643 DstRC), 3644 [HasMSA, IsBE]>; 3645 3646 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT, 3647 RegisterClass DstRC> : 3648 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3649 3650 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT, 3651 RegisterClass DstRC> : 3652 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>; 3653 3654 class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT, 3655 RegisterClass DstRC> : 3656 MSAPat<(DstVT (bitconvert SrcVT:$src)), 3657 (COPY_TO_REGCLASS 3658 (SHF_W 3659 (COPY_TO_REGCLASS 3660 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27), 3661 MSA128W), 177), 3662 DstRC), 3663 [HasMSA, IsBE]>; 3664 3665 class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT, 3666 RegisterClass DstRC> : 3667 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3668 3669 class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT, 3670 RegisterClass DstRC> : 3671 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>; 3672 3673 class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT, 3674 RegisterClass DstRC> : 3675 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>; 3676 3677 def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>; 3678 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; 3679 def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>; 3680 def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>; 3681 def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>; 3682 def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>; 3683 3684 def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>; 3685 def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>; 3686 def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>; 3687 def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>; 3688 def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>; 3689 3690 def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>; 3691 def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>; 3692 def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>; 3693 def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>; 3694 def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>; 3695 3696 def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>; 3697 def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>; 3698 def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>; 3699 def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>; 3700 def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>; 3701 3702 def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>; 3703 def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>; 3704 def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>; 3705 def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>; 3706 def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>; 3707 3708 def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>; 3709 def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>; 3710 def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>; 3711 def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>; 3712 def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>; 3713 3714 def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>; 3715 def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>; 3716 def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>; 3717 def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>; 3718 def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>; 3719 3720 // Pseudos used to implement BNZ.df, and BZ.df 3721 3722 class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode, 3723 RegisterClass RCWS, 3724 InstrItinClass itin = NoItinerary> : 3725 MipsPseudo<(outs GPR32:$dst), 3726 (ins RCWS:$ws), 3727 [(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> { 3728 bit usesCustomInserter = 1; 3729 } 3730 3731 def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8, 3732 MSA128B, NoItinerary>; 3733 def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16, 3734 MSA128H, NoItinerary>; 3735 def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32, 3736 MSA128W, NoItinerary>; 3737 def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64, 3738 MSA128D, NoItinerary>; 3739 def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8, 3740 MSA128B, NoItinerary>; 3741 3742 def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8, 3743 MSA128B, NoItinerary>; 3744 def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16, 3745 MSA128H, NoItinerary>; 3746 def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32, 3747 MSA128W, NoItinerary>; 3748 def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, 3749 MSA128D, NoItinerary>; 3750 def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, 3751 MSA128B, NoItinerary>; 3752 3753 // Pseudoes used to implement transparent fp16 support. 3754 3755 let ASEPredicate = [HasMSA] in { 3756 def ST_F16 : MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr), 3757 [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]> { 3758 let usesCustomInserter = 1; 3759 } 3760 3761 def LD_F16 : MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr), 3762 [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]> { 3763 let usesCustomInserter = 1; 3764 } 3765 3766 def MSA_FP_EXTEND_W_PSEUDO : MipsPseudo<(outs FGR32Opnd:$fd), 3767 (ins MSA128F16:$ws), 3768 [(set FGR32Opnd:$fd, 3769 (f32 (fpextend MSA128F16:$ws)))]> { 3770 let usesCustomInserter = 1; 3771 } 3772 3773 def MSA_FP_ROUND_W_PSEUDO : MipsPseudo<(outs MSA128F16:$wd), 3774 (ins FGR32Opnd:$fs), 3775 [(set MSA128F16:$wd, 3776 (f16 (fpround FGR32Opnd:$fs)))]> { 3777 let usesCustomInserter = 1; 3778 } 3779 3780 def MSA_FP_EXTEND_D_PSEUDO : MipsPseudo<(outs FGR64Opnd:$fd), 3781 (ins MSA128F16:$ws), 3782 [(set FGR64Opnd:$fd, 3783 (f64 (fpextend MSA128F16:$ws)))]> { 3784 let usesCustomInserter = 1; 3785 } 3786 3787 def MSA_FP_ROUND_D_PSEUDO : MipsPseudo<(outs MSA128F16:$wd), 3788 (ins FGR64Opnd:$fs), 3789 [(set MSA128F16:$wd, 3790 (f16 (fpround FGR64Opnd:$fs)))]> { 3791 let usesCustomInserter = 1; 3792 } 3793 3794 def : MipsPat<(MipsTruncIntFP MSA128F16:$ws), 3795 (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>, ISA_MIPS1, 3796 ASE_MSA; 3797 3798 def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond), 3799 (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws), 3800 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>, 3801 ISA_MIPS1_NOT_32R6_64R6, ASE_MSA; 3802 } 3803 3804 def vsplati64_imm_eq_63 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ 3805 APInt Imm; 3806 SDNode *BV = N->getOperand(0).getNode(); 3807 EVT EltTy = N->getValueType(0).getVectorElementType(); 3808 3809 return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && 3810 Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 63; 3811 }]>; 3812 3813 def immi32Cst7 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 7;}]>; 3814 def immi32Cst15 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 15;}]>; 3815 def immi32Cst31 : ImmLeaf<i32, [{return isUInt<32>(Imm) && Imm == 31;}]>; 3816 3817 def vsplati8imm7 : PatFrag<(ops node:$wt), 3818 (and node:$wt, (vsplati8 immi32Cst7))>; 3819 def vsplati16imm15 : PatFrag<(ops node:$wt), 3820 (and node:$wt, (vsplati16 immi32Cst15))>; 3821 def vsplati32imm31 : PatFrag<(ops node:$wt), 3822 (and node:$wt, (vsplati32 immi32Cst31))>; 3823 def vsplati64imm63 : PatFrag<(ops node:$wt), 3824 (and node:$wt, vsplati64_imm_eq_63)>; 3825 3826 class MSAShiftPat<SDNode Node, ValueType VT, MSAInst Insn, dag Vec> : 3827 MSAPat<(VT (Node VT:$ws, (VT (and VT:$wt, Vec)))), 3828 (VT (Insn VT:$ws, VT:$wt))>; 3829 3830 class MSABitPat<SDNode Node, ValueType VT, MSAInst Insn, PatFrag Frag> : 3831 MSAPat<(VT (Node VT:$ws, (shl vsplat_imm_eq_1, (Frag VT:$wt)))), 3832 (VT (Insn VT:$ws, VT:$wt))>; 3833 3834 multiclass MSAShiftPats<SDNode Node, string Insn> { 3835 def : MSAShiftPat<Node, v16i8, !cast<MSAInst>(Insn#_B), 3836 (vsplati8 immi32Cst7)>; 3837 def : MSAShiftPat<Node, v8i16, !cast<MSAInst>(Insn#_H), 3838 (vsplati16 immi32Cst15)>; 3839 def : MSAShiftPat<Node, v4i32, !cast<MSAInst>(Insn#_W), 3840 (vsplati32 immi32Cst31)>; 3841 def : MSAPat<(v2i64 (Node v2i64:$ws, (v2i64 (and v2i64:$wt, 3842 vsplati64_imm_eq_63)))), 3843 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>; 3844 } 3845 3846 multiclass MSABitPats<SDNode Node, string Insn> { 3847 def : MSABitPat<Node, v16i8, !cast<MSAInst>(Insn#_B), vsplati8imm7>; 3848 def : MSABitPat<Node, v8i16, !cast<MSAInst>(Insn#_H), vsplati16imm15>; 3849 def : MSABitPat<Node, v4i32, !cast<MSAInst>(Insn#_W), vsplati32imm31>; 3850 def : MSAPat<(Node v2i64:$ws, (shl (v2i64 vsplati64_imm_eq_1), 3851 (vsplati64imm63 v2i64:$wt))), 3852 (v2i64 (!cast<MSAInst>(Insn#_D) v2i64:$ws, v2i64:$wt))>; 3853 } 3854 3855 defm : MSAShiftPats<shl, "SLL">; 3856 defm : MSAShiftPats<srl, "SRL">; 3857 defm : MSAShiftPats<sra, "SRA">; 3858 defm : MSABitPats<xor, "BNEG">; 3859 defm : MSABitPats<or, "BSET">; 3860 3861 def : MSAPat<(and v16i8:$ws, (xor (shl vsplat_imm_eq_1, 3862 (vsplati8imm7 v16i8:$wt)), 3863 immAllOnesV)), 3864 (v16i8 (BCLR_B v16i8:$ws, v16i8:$wt))>; 3865 def : MSAPat<(and v8i16:$ws, (xor (shl vsplat_imm_eq_1, 3866 (vsplati16imm15 v8i16:$wt)), 3867 immAllOnesV)), 3868 (v8i16 (BCLR_H v8i16:$ws, v8i16:$wt))>; 3869 def : MSAPat<(and v4i32:$ws, (xor (shl vsplat_imm_eq_1, 3870 (vsplati32imm31 v4i32:$wt)), 3871 immAllOnesV)), 3872 (v4i32 (BCLR_W v4i32:$ws, v4i32:$wt))>; 3873 def : MSAPat<(and v2i64:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1), 3874 (vsplati64imm63 v2i64:$wt)), 3875 (bitconvert (v4i32 immAllOnesV)))), 3876 (v2i64 (BCLR_D v2i64:$ws, v2i64:$wt))>; 3877 3878 // Vector extraction with fixed index. 3879 // 3880 // Extracting 32-bit values on MSA32 should always use COPY_S_W rather than 3881 // COPY_U_W, even for the zero-extended case. This is because our forward 3882 // compatibility strategy is to consider registers to be infinitely 3883 // sign-extended so that a MIPS64 can execute MIPS32 code without getting 3884 // different register values. 3885 def : MSAPat<(vextract_zext_i32 (v4i32 MSA128W:$ws), immZExt2Ptr:$idx), 3886 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3887 def : MSAPat<(vextract_zext_i32 (v4f32 MSA128W:$ws), immZExt2Ptr:$idx), 3888 (COPY_S_W MSA128W:$ws, immZExt2:$idx)>, ASE_MSA_NOT_MSA64; 3889 3890 // Extracting 64-bit values on MSA64 should always use COPY_S_D rather than 3891 // COPY_U_D, even for the zero-extended case. This is because our forward 3892 // compatibility strategy is to consider registers to be infinitely 3893 // sign-extended so that a hypothetical MIPS128 would be able to execute MIPS64 3894 // code without getting different register values. 3895 def : MSAPat<(vextract_zext_i64 (v2i64 MSA128D:$ws), immZExt1Ptr:$idx), 3896 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3897 def : MSAPat<(vextract_zext_i64 (v2f64 MSA128D:$ws), immZExt1Ptr:$idx), 3898 (COPY_S_D MSA128D:$ws, immZExt1:$idx)>, ASE_MSA64; 3899 3900 // Vector extraction with variable index 3901 def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)), 3902 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3903 i32:$idx), 3904 sub_lo)), 3905 GPR32), (i32 24))>; 3906 def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)), 3907 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3908 i32:$idx), 3909 sub_lo)), 3910 GPR32), (i32 16))>; 3911 def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)), 3912 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3913 i32:$idx), 3914 sub_lo)), 3915 GPR32)>; 3916 def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)), 3917 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3918 i32:$idx), 3919 sub_64)), 3920 GPR64), [HasMSA, IsGP64bit]>; 3921 3922 def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)), 3923 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws, 3924 i32:$idx), 3925 sub_lo)), 3926 GPR32), (i32 24))>; 3927 def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)), 3928 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws, 3929 i32:$idx), 3930 sub_lo)), 3931 GPR32), (i32 16))>; 3932 def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)), 3933 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws, 3934 i32:$idx), 3935 sub_lo)), 3936 GPR32)>; 3937 def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)), 3938 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws, 3939 i32:$idx), 3940 sub_64)), 3941 GPR64), [HasMSA, IsGP64bit]>; 3942 3943 def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)), 3944 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws, 3945 i32:$idx), 3946 sub_lo))>; 3947 def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)), 3948 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws, 3949 i32:$idx), 3950 sub_64))>; 3951 3952 // Vector extraction with variable index (N64 ABI) 3953 def : MSAPat< 3954 (i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)), 3955 (SRA (COPY_TO_REGCLASS 3956 (i32 (EXTRACT_SUBREG 3957 (SPLAT_B v16i8:$ws, 3958 (COPY_TO_REGCLASS 3959 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3960 sub_lo)), 3961 GPR32), 3962 (i32 24))>; 3963 def : MSAPat< 3964 (i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)), 3965 (SRA (COPY_TO_REGCLASS 3966 (i32 (EXTRACT_SUBREG 3967 (SPLAT_H v8i16:$ws, 3968 (COPY_TO_REGCLASS 3969 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3970 sub_lo)), 3971 GPR32), 3972 (i32 16))>; 3973 def : MSAPat< 3974 (i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)), 3975 (COPY_TO_REGCLASS 3976 (i32 (EXTRACT_SUBREG 3977 (SPLAT_W v4i32:$ws, 3978 (COPY_TO_REGCLASS 3979 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3980 sub_lo)), 3981 GPR32)>; 3982 def : MSAPat< 3983 (i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)), 3984 (COPY_TO_REGCLASS 3985 (i64 (EXTRACT_SUBREG 3986 (SPLAT_D v2i64:$ws, 3987 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3988 sub_64)), 3989 GPR64), [HasMSA, IsGP64bit]>; 3990 3991 def : MSAPat< 3992 (i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)), 3993 (SRL (COPY_TO_REGCLASS 3994 (i32 (EXTRACT_SUBREG 3995 (SPLAT_B v16i8:$ws, 3996 (COPY_TO_REGCLASS 3997 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 3998 sub_lo)), 3999 GPR32), 4000 (i32 24))>; 4001 def : MSAPat< 4002 (i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)), 4003 (SRL (COPY_TO_REGCLASS 4004 (i32 (EXTRACT_SUBREG 4005 (SPLAT_H v8i16:$ws, 4006 (COPY_TO_REGCLASS 4007 (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4008 sub_lo)), 4009 GPR32), 4010 (i32 16))>; 4011 def : MSAPat< 4012 (i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)), 4013 (COPY_TO_REGCLASS 4014 (i32 (EXTRACT_SUBREG 4015 (SPLAT_W v4i32:$ws, 4016 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4017 sub_lo)), 4018 GPR32)>; 4019 def : MSAPat< 4020 (i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)), 4021 (COPY_TO_REGCLASS 4022 (i64 (EXTRACT_SUBREG 4023 (SPLAT_D v2i64:$ws, 4024 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4025 sub_64)), 4026 GPR64), 4027 [HasMSA, IsGP64bit]>; 4028 4029 def : MSAPat< 4030 (f32 (vector_extract v4f32:$ws, i64:$idx)), 4031 (f32 (EXTRACT_SUBREG 4032 (SPLAT_W v4f32:$ws, 4033 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4034 sub_lo))>; 4035 def : MSAPat< 4036 (f64 (vector_extract v2f64:$ws, i64:$idx)), 4037 (f64 (EXTRACT_SUBREG 4038 (SPLAT_D v2f64:$ws, 4039 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)), 4040 sub_64))>; 4041
