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      1 //===-- MipsMTInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 //===----------------------------------------------------------------------===//
     11 //  Describe the MIPS MT instructions format
     12 //
     13 //  opcode - operation code.
     14 //  rt     - destination register
     15 //
     16 //===----------------------------------------------------------------------===//
     17 
     18 class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
     19   let DecoderNamespace = "Mips";
     20   let EncodingPredicates = [HasStdEnc];
     21 }
     22 
     23 class OPCODE1<bits<1> Val> {
     24   bits<1> Value = Val;
     25 }
     26 
     27 def OPCODE_SC_D : OPCODE1<0b0>;
     28 def OPCODE_SC_E : OPCODE1<0b1>;
     29 
     30 class FIELD5<bits<5> Val> {
     31   bits<5> Value = Val;
     32 }
     33 
     34 def FIELD5_1_DMT_EMT  : FIELD5<0b00001>;
     35 def FIELD5_2_DMT_EMT  : FIELD5<0b01111>;
     36 def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
     37 def FIELD5_MFTR : FIELD5<0b01000>;
     38 def FIELD5_MTTR : FIELD5<0b01100>;
     39 
     40 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
     41   bits<32> Inst;
     42 
     43   bits<5> rt;
     44   let Inst{31-26} = 0b010000; // COP0
     45   let Inst{25-21} = 0b01011;  // MFMC0
     46   let Inst{20-16} = rt;
     47   let Inst{15-11} = Op1.Value;
     48   let Inst{10-6}  = Op2.Value;
     49   let Inst{5}     = sc.Value;
     50   let Inst{4-3}   = 0b00;
     51   let Inst{2-0}   = 0b001;
     52 }
     53 
     54 class COP0_MFTTR_MT<FIELD5 Op> : MipsMTInst {
     55   bits<32> Inst;
     56 
     57   bits<5> rt;
     58   bits<5> rd;
     59   bits<1> u;
     60   bits<1> h;
     61   bits<3> sel;
     62   let Inst{31-26} = 0b010000; // COP0
     63   let Inst{25-21} = Op.Value; // MFMC0
     64   let Inst{20-16} = rt;
     65   let Inst{15-11} = rd;
     66   let Inst{10-6}  = 0b00000;  // rx - currently unsupported.
     67   let Inst{5}     = u;
     68   let Inst{4}     = h;
     69   let Inst{3}     = 0b0;
     70   let Inst{2-0}   = sel;
     71 }
     72 
     73 class SPECIAL3_MT_FORK : MipsMTInst {
     74   bits<32> Inst;
     75 
     76   bits<5> rs;
     77   bits<5> rt;
     78   bits<5> rd;
     79   let Inst{31-26} = 0b011111; // SPECIAL3
     80   let Inst{25-21} = rs;
     81   let Inst{20-16} = rt;
     82   let Inst{15-11} = rd;
     83   let Inst{10-6}  = 0b00000;
     84   let Inst{5-0}   = 0b001000; // FORK
     85 }
     86 
     87 class SPECIAL3_MT_YIELD : MipsMTInst {
     88   bits<32> Inst;
     89 
     90   bits<5> rs;
     91   bits<5> rd;
     92   let Inst{31-26} = 0b011111; // SPECIAL3
     93   let Inst{25-21} = rs;
     94   let Inst{20-16} = 0b00000;
     95   let Inst{15-11} = rd;
     96   let Inst{10-6}  = 0b00000;
     97   let Inst{5-0}   = 0b001001; // FORK
     98 }
     99