1 //=- MipsScheduleGeneric.td - Generic Scheduling Definitions -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the interAptiv processor in a manner of speaking. It 11 // describes a hypothetical version of the in-order MIPS32R2 interAptiv with all 12 // branches of the MIPS ISAs, ASEs and ISA variants. The itinerary lists are 13 // broken down into per ISA lists, so that this file can be used to rapidly 14 // develop new schedule models. 15 // 16 //===----------------------------------------------------------------------===// 17 def MipsGenericModel : SchedMachineModel { 18 int IssueWidth = 1; 19 int MicroOpBufferSize = 0; 20 21 // These figures assume an L1 hit. 22 int LoadLatency = 2; 23 int MispredictPenalty = 4; 24 25 int HighLatency = 37; 26 list<Predicate> UnsupportedFeatures = []; 27 28 let CompleteModel = 0; 29 let PostRAScheduler = 1; 30 31 // FIXME: Remove when all errors have been fixed. 32 let FullInstRWOverlapCheck = 0; 33 } 34 35 let SchedModel = MipsGenericModel in { 36 37 // ALU Pipeline 38 // ============ 39 40 def GenericALU : ProcResource<1> { let BufferSize = 1; } 41 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; } 42 43 def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>; 44 45 // and, lui, nor, or, slti, sltiu, sub, subu, xor 46 // add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu, 47 // xori 48 def : ItinRW<[GenericWriteALU], [II_ADD, II_ADDU, II_ADDI, II_ADDIU, II_ANDI, 49 II_AND, II_ANDI, II_CLO, II_CLZ, II_EXT, 50 II_INS, II_LUI, II_MULT, II_MULTU, II_NOR, 51 II_ORI, II_OR, II_ROTR, II_ROTRV, II_SEB, 52 II_SEH, II_SLTI_SLTIU, II_SLT_SLTU, II_SLL, 53 II_SRA, II_SRL, II_SLLV, II_SRAV, II_SRLV, 54 II_SSNOP, II_SUB, II_SUBU, II_WSBH, II_XOR, 55 II_XORI]>; 56 57 def : InstRW<[GenericWriteALU], (instrs COPY)>; 58 59 def GenericMDU : ProcResource<1> { let BufferSize = 1; } 60 def GenericIssueMDU : ProcResource<1> { let Super = GenericALU; } 61 def GenericIssueDIV : ProcResource<1> { let Super = GenericMDU; } 62 def GenericWriteHILO : SchedWriteRes<[GenericIssueMDU]>; 63 def GenericWriteALULong : SchedWriteRes<[GenericIssueALU]> { let Latency = 5; } 64 def GenericWriteMove : SchedWriteRes<[GenericIssueALU]> { let Latency = 2; } 65 66 def : ItinRW<[GenericWriteHILO], [II_MADD, II_MADDU, II_MSUB, II_MSUBU]>; 67 68 def GenericWriteMDUtoGPR : SchedWriteRes<[GenericIssueMDU]> { 69 let Latency = 5; 70 } 71 72 def : ItinRW<[GenericWriteMDUtoGPR], [II_MUL]>; 73 74 def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> { 75 // Estimated worst case 76 let Latency = 33; 77 let ResourceCycles = [33]; 78 } 79 def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> { 80 // Estimated worst case 81 let Latency = 31; 82 let ResourceCycles = [31]; 83 } 84 85 def : ItinRW<[GenericWriteDIV], [II_DIV]>; 86 87 def : ItinRW<[GenericWriteDIVU], [II_DIVU]>; 88 89 // MIPS64 90 // ====== 91 92 def : ItinRW<[GenericWriteALU], [II_DADDIU, II_DADDU, II_DADDI, II_DADD, 93 II_DCLO, II_DCLZ, II_DROTR, II_DROTR32, 94 II_DROTRV, II_DSBH, II_DSHD, II_DSLL, 95 II_DSLL32, II_DSLLV, II_DSRA, II_DSRA32, 96 II_DSRAV, II_DSRL, II_DSRL32, II_DSRLV, 97 II_DSUBU, II_DSUB]>; 98 99 def : ItinRW<[GenericWriteDIV], [II_DDIV]>; 100 101 def : ItinRW<[GenericWriteDIVU], [II_DDIVU]>; 102 103 def : ItinRW<[GenericWriteMDUtoGPR], [II_DMUL]>; 104 105 def : ItinRW<[GenericWriteHILO], [II_DMULU, II_DMULT, II_DMULTU]>; 106 107 // MIPS16e 108 // ======= 109 110 def : ItinRW<[GenericWriteALU], [IIM16Alu, IIPseudo]>; 111 112 // microMIPS 113 // ========= 114 115 def : ItinRW<[GenericWriteALU], [II_MOVE, II_LI, II_NOT]>; 116 117 // MIPSR6 118 // ====== 119 120 def GenericWriteMul : SchedWriteRes<[GenericIssueMDU]> { let Latency = 4; } 121 def : ItinRW<[GenericWriteMul], [II_MUH, II_MUHU, II_MULU]>; 122 123 def : ItinRW<[GenericWriteDIV], [II_MOD, II_MODU]>; 124 125 def : ItinRW<[GenericWriteALU], [II_ADDIUPC, II_ALIGN, II_ALUIPC, II_AUI, 126 II_AUIPC, II_BITSWAP, II_LSA, II_SELCCZ]>; 127 128 // MIPS64R6 129 // ======== 130 131 def : ItinRW<[GenericWriteALU], [II_DALIGN, II_DAHI, II_DATI, II_DAUI, 132 II_DBITSWAP, II_DLSA]>; 133 134 def : ItinRW<[GenericWriteMDUtoGPR], [II_DMUH, II_DMUHU]>; 135 def : ItinRW<[GenericWriteDIV], [II_DMOD, II_DMODU]>; 136 137 // clo, clz, di, mfhi, mflo 138 def : ItinRW<[GenericWriteALULong], [II_MFHI_MFLO]>; 139 def : ItinRW<[GenericWriteALU], [II_MOVN, II_MOVZ]>; 140 def : ItinRW<[GenericWriteMove], [II_MTHI_MTLO, II_RDHWR]>; 141 142 143 // CTISTD Pipeline 144 // --------------- 145 146 def GenericIssueCTISTD : ProcResource<1> { let Super = GenericALU; } 147 148 def GenericLDST : ProcResource<1> { let BufferSize = 1; } 149 def GenericIssueLDST : ProcResource<1> { let Super = GenericLDST; } 150 151 def GenericWriteJump : SchedWriteRes<[GenericIssueCTISTD]>; 152 def GenericWriteJumpAndLink : SchedWriteRes<[GenericIssueCTISTD]> { 153 let Latency = 2; 154 } 155 156 // b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, jalx, 157 // jalr, jr.hb, jr, jalr.hb, jarlc, jialc 158 def : ItinRW<[GenericWriteJump], [II_B, II_BCC, II_BCCZ, II_BCCZAL, II_J, 159 II_JR, II_JR_HB, II_ERET, II_ERETNC, 160 II_DERET]>; 161 162 def : ItinRW<[GenericWriteJumpAndLink], [II_JAL, II_JALR, II_JALR_HB, 163 II_BC2CCZ]>; 164 165 def : ItinRW<[GenericWriteJump], [II_JRC, II_JRADDIUSP]>; 166 167 def : ItinRW<[GenericWriteJumpAndLink], [II_BCCZALS, II_JALS, II_JALRS]>; 168 169 // MIPSR6 170 // ====== 171 172 def : ItinRW<[GenericWriteJumpAndLink], [II_BALC, II_JALRC, II_JIALC]>; 173 174 def : ItinRW<[GenericWriteJump], [II_JIC, II_BC, II_BCCC, II_BCCZC]>; 175 176 177 def GenericWriteTrap : SchedWriteRes<[GenericIssueCTISTD]>; 178 179 def : ItinRW<[GenericWriteTrap], [II_BREAK, II_SYSCALL, II_TEQ, II_TEQI, 180 II_TGE, II_TGEI, II_TGEIU, II_TGEU, II_TNE, 181 II_TNEI, II_TLT, II_TLTI, II_TLTU, II_TTLTIU, 182 II_TRAP, II_SDBBP]>; 183 184 // COP0 Pipeline 185 // ============= 186 187 def GenericCOP0 : ProcResource<1> { let BufferSize = 1; } 188 189 def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; } 190 def GenericWriteCOP0TLB : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 4; } 191 def GenericWriteCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 3; } 192 def GenericReadCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 2; } 193 def GenericReadWritePGPR : SchedWriteRes<[GenericIssueCOP0]>; 194 def GenericReadWriteCOP0Long : SchedWriteRes<[GenericIssueCOP0]> { 195 let Latency = 5; 196 } 197 def GenericWriteCOP0Short : SchedWriteRes<[GenericIssueCOP0]>; 198 199 def : ItinRW<[GenericWriteCOP0TLB], [II_TLBP, II_TLBR, II_TLBWI, II_TLBWR]>; 200 def : ItinRW<[GenericWriteCOP0TLB], [II_TLBINV, II_TLBINVF]>; 201 202 def : ItinRW<[GenericReadCOP0], [II_MFC0]>; 203 def : ItinRW<[GenericWriteCOP0], [II_MTC0]>; 204 205 def : ItinRW<[GenericWriteCOP0], [II_EVP, II_DVP]>; 206 207 // MIPSR5 208 // ====== 209 def : ItinRW<[GenericReadCOP0], [II_MFHC0]>; 210 def : ItinRW<[GenericWriteCOP0], [II_MTHC0]>; 211 212 // MIPS64 213 // ====== 214 215 def : ItinRW<[GenericReadCOP0], [II_DMFC0]>; 216 def : ItinRW<[GenericWriteCOP0], [II_DMTC0]>; 217 218 def : ItinRW<[GenericWriteCOP0], [II_RDPGPR, II_WRPGPR]>; 219 220 def : ItinRW<[GenericWriteCOP0], [II_DI, II_EI]>; 221 222 def : ItinRW<[GenericWriteCOP0], [II_EHB, II_PAUSE, II_WAIT]>; 223 224 def GenericCOP2 : ProcResource<1> { let BufferSize = 1; } 225 def GenericWriteCOPOther : SchedWriteRes<[GenericCOP2]>; 226 227 def : ItinRW<[GenericWriteCOPOther], [II_MFC2, II_MTC2, II_DMFC2, II_DMTC2]>; 228 229 // LDST Pipeline 230 // ------------- 231 232 def GenericWriteLoad : SchedWriteRes<[GenericIssueLDST]> { 233 let Latency = 2; 234 } 235 236 def GenericWritePref : SchedWriteRes<[GenericIssueLDST]>; 237 def GenericWriteSync : SchedWriteRes<[GenericIssueLDST]>; 238 def GenericWriteCache : SchedWriteRes<[GenericIssueLDST]> { let Latency = 5; } 239 240 def GenericWriteStore : SchedWriteRes<[GenericIssueLDST]>; 241 def GenericWriteStoreSC : SchedWriteRes<[GenericIssueLDST]> { let Latency = 2; } 242 243 def GenericWriteGPRFromBypass : SchedWriteRes<[GenericIssueLDST]> { 244 let Latency = 2; 245 } 246 247 def GenericWriteStoreFromOtherUnits : SchedWriteRes<[GenericIssueLDST]>; 248 def GenericWriteLoadToOtherUnits : SchedWriteRes<[GenericIssueLDST]> { 249 let Latency = 0; 250 } 251 252 // l[bhw], l[bh]u, ll 253 def : ItinRW<[GenericWriteLoad], [II_LB, II_LBU, II_LH, II_LHU, II_LW, II_LL, 254 II_LWC2, II_LWC3, II_LDC2, II_LDC3]>; 255 256 // lw[lr] 257 def : ItinRW<[GenericWriteLoad], [II_LWL, II_LWR]>; 258 259 // MIPS64 loads 260 def : ItinRW<[GenericWriteLoad], [II_LD, II_LLD, II_LWU]>; 261 262 // ld[lr] 263 def : ItinRW<[GenericWriteLoad], [II_LDL, II_LDR]>; 264 265 // MIPS32 EVA 266 def : ItinRW<[GenericWriteLoad], [II_LBE, II_LBUE, II_LHE, II_LHUE, II_LWE, 267 II_LLE]>; 268 269 def : ItinRW<[GenericWriteLoad], [II_LWLE, II_LWRE]>; 270 271 // MIPS MT instructions 272 // ==================== 273 274 def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE, II_MFTR, 275 II_MTTR]>; 276 277 def : ItinRW<[GenericReadWriteCOP0Long], [II_YIELD]>; 278 279 def : ItinRW<[GenericWriteCOP0Short], [II_FORK]>; 280 281 // MIPS32R6 and MIPS16e 282 // ==================== 283 284 def : ItinRW<[GenericWriteLoad], [II_LWPC]>; 285 286 // MIPS64R6 287 // ==================== 288 289 def : ItinRW<[GenericWriteLoad], [II_LWUPC, II_LDPC]>; 290 291 292 // s[bhw], sc, s[dw]c[23] 293 def : ItinRW<[GenericWriteStore], [II_SB, II_SH, II_SW, II_SWC2, II_SWC3, 294 II_SDC2, II_SDC3]>; 295 296 def : ItinRW<[GenericWriteStoreSC], [II_SC]>; 297 298 // PreMIPSR6 sw[lr] 299 def : ItinRW<[GenericWriteStore], [II_SWL, II_SWR]>; 300 301 // EVA ASE stores 302 def : ItinRW<[GenericWriteStore], [II_SBE, II_SHE, II_SWE, II_SCE]>; 303 304 def : ItinRW<[GenericWriteStore], [II_SWLE, II_SWRE]>; 305 306 // MIPS64 307 // ====== 308 309 def : ItinRW<[GenericWriteStore], [II_SD, II_SCD]>; 310 311 // PreMIPSR6 stores 312 // ================ 313 314 def : ItinRW<[GenericWriteStore], [II_SDL, II_SDR]>; 315 316 // MIPS16e 317 // ======= 318 319 def : ItinRW<[GenericWriteLoad], [II_RESTORE]>; 320 321 def : ItinRW<[GenericWriteStore], [II_SAVE]>; 322 323 // microMIPS 324 // ========= 325 326 def : ItinRW<[GenericWriteLoad], [II_LWM, II_LWP, II_LWXS]>; 327 328 def : ItinRW<[GenericWriteStore], [II_SWM, II_SWP]>; 329 330 // pref 331 def : ItinRW<[GenericWritePref], [II_PREF]>; 332 333 def : ItinRW<[GenericWritePref], [II_PREFE]>; 334 335 // cache 336 def : ItinRW<[GenericWriteCache], [II_CACHE]>; 337 338 def : ItinRW<[GenericWriteCache], [II_CACHEE]>; 339 340 // sync 341 def : ItinRW<[GenericWriteSync], [II_SYNC]>; 342 343 def : ItinRW<[GenericWriteSync], [II_SYNCI]>; 344 345 // FPU Pipelines 346 // ============= 347 348 def GenericFPQ : ProcResource<1> { let BufferSize = 1; } 349 def GenericIssueFPUS : ProcResource<1> { let Super = GenericFPQ; } 350 def GenericIssueFPUL : ProcResource<1> { let Super = GenericFPQ; } 351 def GenericIssueFPULoad : ProcResource<1> { let Super = GenericFPQ; } 352 def GenericIssueFPUStore : ProcResource<1> { let Super = GenericFPQ; } 353 def GenericIssueFPUMove : ProcResource<1> { let Super = GenericFPQ; } 354 def GenericFPUDivSqrt : ProcResource<1> { let Super = GenericFPQ; } 355 356 // The floating point compare of the 24k series including interAptiv has a 357 // listed latency of 1-2. Using the higher latency here. 358 359 def GenericWriteFPUCmp : SchedWriteRes<[GenericIssueFPUS]> { let Latency = 2; } 360 def GenericWriteFPUS : SchedWriteRes<[GenericIssueFPUS]> { let Latency = 4; } 361 def GenericWriteFPUL : SchedWriteRes<[GenericIssueFPUL]> { let Latency = 5; } 362 def GenericWriteFPUStore : SchedWriteRes<[GenericIssueFPUStore]> { let 363 Latency = 1; 364 } 365 def GenericWriteFPULoad : SchedWriteRes<[GenericIssueFPULoad]> { 366 let Latency = 2; 367 } 368 def GenericWriteFPUMoveFP : SchedWriteRes<[GenericIssueFPUMove]> { 369 let Latency = 4; 370 } 371 def GenericWriteFPUMoveGPRFPU : SchedWriteRes<[GenericIssueFPUMove]> { 372 let Latency = 2; 373 } 374 def GenericWriteFPUDivS : SchedWriteRes<[GenericFPUDivSqrt]> { 375 let Latency = 17; 376 let ResourceCycles = [ 14 ]; 377 } 378 def GenericWriteFPUDivD : SchedWriteRes<[GenericFPUDivSqrt]> { 379 let Latency = 32; 380 let ResourceCycles = [ 29 ]; 381 } 382 def GenericWriteFPURcpS : SchedWriteRes<[GenericFPUDivSqrt]> { 383 let Latency = 13; 384 let ResourceCycles = [ 10 ]; 385 } 386 def GenericWriteFPURcpD : SchedWriteRes<[GenericFPUDivSqrt]> { 387 let Latency = 25; 388 let ResourceCycles = [ 21 ]; 389 } 390 def GenericWriteFPURsqrtS : SchedWriteRes<[GenericFPUDivSqrt]> { 391 let Latency = 17; 392 let ResourceCycles = [ 14 ]; 393 } 394 def GenericWriteFPURsqrtD : SchedWriteRes<[GenericFPUDivSqrt]> { 395 let Latency = 32; 396 let ResourceCycles = [ 29 ]; 397 } 398 def GenericWriteFPUSqrtS : SchedWriteRes<[GenericFPUDivSqrt]> { 399 let Latency = 17; 400 let ResourceCycles = [ 14 ]; 401 } 402 def GenericWriteFPUSqrtD : SchedWriteRes<[GenericFPUDivSqrt]> { 403 let Latency = 29; 404 let ResourceCycles = [ 29 ]; 405 } 406 407 // Floating point compare and branch 408 // --------------------------------- 409 // 410 // c.<cc>.[ds], bc1[tf], bc1[tf]l 411 def : ItinRW<[GenericWriteFPUCmp], [II_C_CC_D, II_C_CC_S, II_BC1F, II_BC1T, 412 II_BC1FL, II_BC1TL]>; 413 414 def : ItinRW<[GenericWriteFPUCmp], [II_CMP_CC_D, II_CMP_CC_S]>; 415 416 // Short Pipe 417 // ---------- 418 // 419 // abs.[ds], abs.ps, add.[ds], neg.[ds], neg.ps, madd.s, msub.s, nmadd,s 420 // nmsub.s, sub.[ds], mul.s 421 422 def : ItinRW<[GenericWriteFPUS], [II_ABS, II_ADD_D, II_ADD_S, II_MADD_S, 423 II_MSUB_S, II_MUL_S, II_NEG, II_NMADD_S, 424 II_NMSUB_S, II_SUB_S, II_SUB_D]>; 425 // mov[tf].[ds] 426 427 def : ItinRW<[GenericWriteFPUS], [II_MOVF_S, II_MOVF_D, II_MOVT_S, II_MOVT_D]>; 428 429 // MIPSR6 430 // ------ 431 // 432 // sel(eq|ne).[ds], max.[ds], maxa.[ds], min.[ds], mina.[ds], class.[ds] 433 def : ItinRW<[GenericWriteFPUS], [II_SELCCZ_S, II_SELCCZ_D, II_MAX_S, 434 II_MAX_D, II_MAXA_S, II_MAXA_D, II_MIN_S, 435 II_MIN_D, II_MINA_S, II_MINA_D, II_CLASS_S, 436 II_CLASS_D]>; 437 438 // Long Pipe 439 // ---------- 440 // 441 // nmadd.d, nmsub.d, mul.[ds], mul.ps, ceil.[wl].[sd], cvt.d.[sw], cvt.s.[dw], 442 // cvt.w.[sd], cvt.[sw].ps, trunc.w.[ds], trunc.w.ps, floor.[ds], 443 // round.[lw].[ds], floor.[lw].ds 444 445 // madd.d, msub.dm mul.d, mul.ps, nmadd.d, nmsub.d, ceil.[wl].[sd], cvt.d.[sw], 446 // cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps, round.[lw].[ds], floor.[lw].ds, 447 // trunc.w.[ds], trunc.w.ps, 448 def : ItinRW<[GenericWriteFPUL], [II_MADD_D, II_MSUB_D, II_MUL_D, II_NMADD_D, 449 II_NMSUB_D, II_CEIL, II_CVT, 450 II_FLOOR, II_ROUND, II_TRUNC]>; 451 452 // div.[ds], div.ps 453 def : ItinRW<[GenericWriteFPUDivS], [II_DIV_S]>; 454 def : ItinRW<[GenericWriteFPUDivD], [II_DIV_D]>; 455 456 // sqrt.[ds], sqrt.ps 457 def : ItinRW<[GenericWriteFPUSqrtS], [II_SQRT_S]>; 458 def : ItinRW<[GenericWriteFPUSqrtD], [II_SQRT_D]>; 459 460 // rsqrt.[ds], recip.[ds] 461 def : ItinRW<[GenericWriteFPURcpS], [II_RECIP_S, II_RSQRT_S]>; 462 def : ItinRW<[GenericWriteFPURcpD], [II_RECIP_D, II_RSQRT_D]>; 463 464 // MIPSR6 465 // ====== 466 // 467 // rint.[ds] 468 def : ItinRW<[GenericWriteFPUL], [II_RINT_S, II_RINT_D]>; 469 470 // Load Pipe 471 // --------- 472 473 // ctc1, mtc1, mthc1, cfc1, mfc1, mfhc1 474 def : ItinRW<[GenericWriteFPUMoveGPRFPU], [II_CFC1, II_CTC1, II_MFC1, II_MFHC1, 475 II_MTC1, II_MTHC1]>; 476 477 // swc1, swxc1 478 def : ItinRW<[GenericWriteFPUStore], [II_SDC1, II_SDXC1, II_SUXC1, II_SWC1, 479 II_SWXC1]>; 480 481 // movn.[ds], movz.[ds] 482 def : ItinRW<[GenericWriteFPUMoveFP], [II_MOV_D, II_MOV_S, II_MOVF, II_MOVT, 483 II_MOVN_D, II_MOVN_S, II_MOVZ_D, 484 II_MOVZ_S]>; 485 486 // l[dw]x?c1 487 def : ItinRW<[GenericWriteFPULoad], [II_LDC1, II_LDXC1, II_LUXC1, II_LWC1, 488 II_LWXC1]>; 489 490 // MIPS64 491 // ====== 492 493 def : ItinRW<[GenericWriteFPUMoveGPRFPU], [II_DMFC1, II_DMTC1]>; 494 495 // MIPSR6 496 // ====== 497 498 def : ItinRW<[GenericWriteFPUS], [II_MADDF_S, II_MSUBF_S]>; 499 500 def : ItinRW<[GenericWriteFPUS], [II_MADDF_D, II_MSUBF_D]>; 501 502 def : ItinRW<[GenericWriteFPUCmp], [II_BC1CCZ, II_SEL_D, II_SEL_S]>; 503 504 // Cavium Networks MIPS (cnMIPS) - Octeon, HasCnMips 505 // ================================================= 506 507 def : ItinRW<[GenericWriteALU], [II_SEQ_SNE, II_SEQI_SNEI, II_POP, II_BADDU, 508 II_BBIT]>; 509 510 // MIPS DSP ASE, HasDSP 511 // ==================== 512 513 def GenericDSP : ProcResource<1> { let BufferSize = 1; } 514 def GenericDSPShort : SchedWriteRes<[GenericDSP]> { let Latency = 2; } 515 def GenericDSPLong : SchedWriteRes<[GenericDSP]> { let Latency = 6; } 516 def GenericDSPBypass : SchedWriteRes<[GenericDSP]> { let Latency = 1; } 517 def GenericDSPMTHILO : SchedWriteRes<[GenericDSP]> { let Latency = 5; } 518 def GenericDSPLoad : SchedWriteRes<[GenericDSP]> { let Latency = 4; } 519 def GenericDSPMTHLIP : SchedWriteRes<[GenericDSP]> { let Latency = 5; } 520 521 def : InstRW<[GenericDSPLong], (instregex "^EXTRV_RS_W$")>; 522 def : InstRW<[GenericDSPLong], (instregex "^EXTRV_R_W$")>; 523 def : InstRW<[GenericDSPLong], (instregex "^EXTRV_S_H$")>; 524 def : InstRW<[GenericDSPLong], (instregex "^EXTRV_W$")>; 525 def : InstRW<[GenericDSPLong], (instregex "^EXTR_RS_W$")>; 526 def : InstRW<[GenericDSPLong], (instregex "^EXTR_R_W$")>; 527 def : InstRW<[GenericDSPLong], (instregex "^EXTR_S_H$")>; 528 def : InstRW<[GenericDSPLong], (instregex "^EXTR_W$")>; 529 def : InstRW<[GenericDSPLong], (instregex "^INSV$")>; 530 531 def : InstRW<[GenericDSPMTHLIP], (instregex "^MTHLIP$")>; 532 def : InstRW<[GenericDSPMTHILO], (instregex "^MTHI_DSP$")>; 533 def : InstRW<[GenericDSPMTHILO], (instregex "^MTLO_DSP$")>; 534 535 def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_PH$")>; 536 def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_W$")>; 537 def : InstRW<[GenericDSPShort], (instregex "^ADDQ_PH$")>; 538 def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_PH$")>; 539 def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_W$")>; 540 def : InstRW<[GenericDSPShort], (instregex "^ADDSC$")>; 541 def : InstRW<[GenericDSPShort], (instregex "^ADDU_QB$")>; 542 def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_QB$")>; 543 def : InstRW<[GenericDSPShort], (instregex "^ADDWC$")>; 544 def : InstRW<[GenericDSPShort], (instregex "^BITREV$")>; 545 def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32$")>; 546 def : InstRW<[GenericDSPShort], (instregex "^CMPGU_EQ_QB$")>; 547 def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LE_QB$")>; 548 def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LT_QB$")>; 549 def : InstRW<[GenericDSPShort], (instregex "^CMPU_EQ_QB$")>; 550 def : InstRW<[GenericDSPShort], (instregex "^CMPU_LE_QB$")>; 551 def : InstRW<[GenericDSPShort], (instregex "^CMPU_LT_QB$")>; 552 def : InstRW<[GenericDSPShort], (instregex "^CMP_EQ_PH$")>; 553 def : InstRW<[GenericDSPShort], (instregex "^CMP_LE_PH$")>; 554 def : InstRW<[GenericDSPShort], (instregex "^CMP_LT_PH$")>; 555 def : InstRW<[GenericDSPShort], (instregex "^DPAQ_SA_L_W$")>; 556 def : InstRW<[GenericDSPShort], (instregex "^DPAQ_S_W_PH$")>; 557 def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBL$")>; 558 def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBR$")>; 559 def : InstRW<[GenericDSPShort], (instregex "^DPSQ_SA_L_W$")>; 560 def : InstRW<[GenericDSPShort], (instregex "^DPSQ_S_W_PH$")>; 561 def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBL$")>; 562 def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBR$")>; 563 def : InstRW<[GenericDSPShort], (instregex "^EXTPDPV$")>; 564 def : InstRW<[GenericDSPShort], (instregex "^EXTPDP$")>; 565 def : InstRW<[GenericDSPShort], (instregex "^EXTPV$")>; 566 def : InstRW<[GenericDSPShort], (instregex "^EXTP$")>; 567 def : InstRW<[GenericDSPShort], (instregex "^LBUX$")>; 568 def : InstRW<[GenericDSPShort], (instregex "^LHX$")>; 569 def : InstRW<[GenericDSPShort], (instregex "^LWX$")>; 570 def : InstRW<[GenericDSPShort], (instregex "^MADDU_DSP$")>; 571 def : InstRW<[GenericDSPShort], (instregex "^MADD_DSP$")>; 572 def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHL$")>; 573 def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHR$")>; 574 def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL$")>; 575 def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR$")>; 576 def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP$")>; 577 def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP$")>; 578 def : InstRW<[GenericDSPShort], (instregex "^MODSUB$")>; 579 def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP$")>; 580 def : InstRW<[GenericDSPShort], (instregex "^MSUB_DSP$")>; 581 def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHL$")>; 582 def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHR$")>; 583 def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBL$")>; 584 def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBR$")>; 585 def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_PH$")>; 586 def : InstRW<[GenericDSPShort], (instregex "^MULSAQ_S_W_PH$")>; 587 def : InstRW<[GenericDSPShort], (instregex "^MULTU_DSP$")>; 588 def : InstRW<[GenericDSPShort], (instregex "^MULT_DSP$")>; 589 def : InstRW<[GenericDSPShort], (instregex "^PACKRL_PH$")>; 590 def : InstRW<[GenericDSPShort], (instregex "^PICK_PH$")>; 591 def : InstRW<[GenericDSPShort], (instregex "^PICK_QB$")>; 592 def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBLA$")>; 593 def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBL$")>; 594 def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBRA$")>; 595 def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBR$")>; 596 def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHL$")>; 597 def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHR$")>; 598 def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBLA$")>; 599 def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBL$")>; 600 def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBRA$")>; 601 def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBR$")>; 602 def : InstRW<[GenericDSPShort], (instregex "^PRECRQU_S_QB_PH$")>; 603 def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_PH_W$")>; 604 def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_QB_PH$")>; 605 def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_RS_PH_W$")>; 606 def : InstRW<[GenericDSPShort], (instregex "^RADDU_W_QB$")>; 607 def : InstRW<[GenericDSPShort], (instregex "^RDDSP$")>; 608 def : InstRW<[GenericDSPShort], (instregex "^REPLV_PH$")>; 609 def : InstRW<[GenericDSPShort], (instregex "^REPLV_QB$")>; 610 def : InstRW<[GenericDSPShort], (instregex "^REPL_PH$")>; 611 def : InstRW<[GenericDSPShort], (instregex "^REPL_QB$")>; 612 def : InstRW<[GenericDSPShort], (instregex "^SHILOV$")>; 613 def : InstRW<[GenericDSPShort], (instregex "^SHILO$")>; 614 def : InstRW<[GenericDSPShort], (instregex "^SHLLV_PH$")>; 615 def : InstRW<[GenericDSPShort], (instregex "^SHLLV_QB$")>; 616 def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_PH$")>; 617 def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_W$")>; 618 def : InstRW<[GenericDSPShort], (instregex "^SHLL_PH$")>; 619 def : InstRW<[GenericDSPShort], (instregex "^SHLL_QB$")>; 620 def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_PH$")>; 621 def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_W$")>; 622 def : InstRW<[GenericDSPShort], (instregex "^SHRAV_PH$")>; 623 def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_PH$")>; 624 def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_W$")>; 625 def : InstRW<[GenericDSPShort], (instregex "^SHRA_PH$")>; 626 def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_PH$")>; 627 def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_W$")>; 628 def : InstRW<[GenericDSPShort], (instregex "^SHRLV_QB$")>; 629 def : InstRW<[GenericDSPShort], (instregex "^SHRL_QB$")>; 630 def : InstRW<[GenericDSPShort], (instregex "^SUBQ_PH$")>; 631 def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_PH$")>; 632 def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_W$")>; 633 def : InstRW<[GenericDSPShort], (instregex "^SUBU_QB$")>; 634 def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_QB$")>; 635 def : InstRW<[GenericDSPShort], (instregex "^WRDSP$")>; 636 637 // MIPS DSP R2 - hasDSP, HasDSPR2, InMicroMips 638 // =========================================== 639 640 def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_QB$")>; 641 def : InstRW<[GenericDSPShort], (instregex "^ADDQH_PH$")>; 642 def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_PH$")>; 643 def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_W$")>; 644 def : InstRW<[GenericDSPShort], (instregex "^ADDQH_W$")>; 645 def : InstRW<[GenericDSPShort], (instregex "^ADDUH_QB$")>; 646 def : InstRW<[GenericDSPShort], (instregex "^ADDUH_R_QB$")>; 647 def : InstRW<[GenericDSPShort], (instregex "^ADDU_PH$")>; 648 def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_PH$")>; 649 def : InstRW<[GenericDSPShort], (instregex "^APPEND$")>; 650 def : InstRW<[GenericDSPShort], (instregex "^BALIGN$")>; 651 def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_EQ_QB$")>; 652 def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LE_QB$")>; 653 def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LT_QB$")>; 654 def : InstRW<[GenericDSPShort], (instregex "^DPA_W_PH$")>; 655 def : InstRW<[GenericDSPShort], (instregex "^DPAQX_SA_W_PH$")>; 656 def : InstRW<[GenericDSPShort], (instregex "^DPAQX_S_W_PH$")>; 657 def : InstRW<[GenericDSPShort], (instregex "^DPAX_W_PH$")>; 658 def : InstRW<[GenericDSPShort], (instregex "^DPS_W_PH$")>; 659 def : InstRW<[GenericDSPShort], (instregex "^DPSQX_S_W_PH$")>; 660 def : InstRW<[GenericDSPShort], (instregex "^DPSQX_SA_W_PH$")>; 661 def : InstRW<[GenericDSPShort], (instregex "^DPSX_W_PH$")>; 662 def : InstRW<[GenericDSPShort], (instregex "^MUL_PH$")>; 663 def : InstRW<[GenericDSPShort], (instregex "^MUL_S_PH$")>; 664 def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_W$")>; 665 def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_PH$")>; 666 def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_W$")>; 667 def : InstRW<[GenericDSPShort], (instregex "^MULSA_W_PH$")>; 668 def : InstRW<[GenericDSPShort], (instregex "^PRECR_QB_PH$")>; 669 def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_PH_W$")>; 670 def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_R_PH_W$")>; 671 def : InstRW<[GenericDSPShort], (instregex "^PREPEND$")>; 672 def : InstRW<[GenericDSPShort], (instregex "^SHRA_QB$")>; 673 def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_QB$")>; 674 def : InstRW<[GenericDSPShort], (instregex "^SHRAV_QB$")>; 675 def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_QB$")>; 676 def : InstRW<[GenericDSPShort], (instregex "^SHRL_PH$")>; 677 def : InstRW<[GenericDSPShort], (instregex "^SHRLV_PH$")>; 678 def : InstRW<[GenericDSPShort], (instregex "^SUBQH_PH$")>; 679 def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_PH$")>; 680 def : InstRW<[GenericDSPShort], (instregex "^SUBQH_W$")>; 681 def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_W$")>; 682 def : InstRW<[GenericDSPShort], (instregex "^SUBU_PH$")>; 683 def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_PH$")>; 684 def : InstRW<[GenericDSPShort], (instregex "^SUBUH_QB$")>; 685 def : InstRW<[GenericDSPShort], (instregex "^SUBUH_R_QB$")>; 686 687 // microMIPS DSP R1 - HasDSP, InMicroMips 688 // ====================================== 689 690 def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_PH_MM$")>; 691 def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_W_MM$")>; 692 def : InstRW<[GenericDSPShort], (instregex "^ADDQ_PH_MM$")>; 693 def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_PH_MM$")>; 694 def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_W_MM$")>; 695 def : InstRW<[GenericDSPShort], (instregex "^ADDSC_MM$")>; 696 def : InstRW<[GenericDSPShort], (instregex "^ADDU_QB_MM$")>; 697 def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_QB_MM$")>; 698 def : InstRW<[GenericDSPShort], (instregex "^ADDWC_MM$")>; 699 def : InstRW<[GenericDSPShort], (instregex "^BITREV_MM$")>; 700 def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32_MM$")>; 701 def : InstRW<[GenericDSPShort], (instregex "^CMPGU_EQ_QB_MM$")>; 702 def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LE_QB_MM$")>; 703 def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LT_QB_MM$")>; 704 def : InstRW<[GenericDSPShort], (instregex "^CMPU_EQ_QB_MM$")>; 705 def : InstRW<[GenericDSPShort], (instregex "^CMPU_LE_QB_MM$")>; 706 def : InstRW<[GenericDSPShort], (instregex "^CMPU_LT_QB_MM$")>; 707 def : InstRW<[GenericDSPShort], (instregex "^CMP_EQ_PH_MM$")>; 708 def : InstRW<[GenericDSPShort], (instregex "^CMP_LE_PH_MM$")>; 709 def : InstRW<[GenericDSPShort], (instregex "^CMP_LT_PH_MM$")>; 710 def : InstRW<[GenericDSPShort], (instregex "^DPAQ_SA_L_W_MM$")>; 711 def : InstRW<[GenericDSPShort], (instregex "^DPAQ_S_W_PH_MM$")>; 712 def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBL_MM$")>; 713 def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBR_MM$")>; 714 def : InstRW<[GenericDSPShort], (instregex "^DPSQ_SA_L_W_MM$")>; 715 def : InstRW<[GenericDSPShort], (instregex "^DPSQ_S_W_PH_MM$")>; 716 def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBL_MM$")>; 717 def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBR_MM$")>; 718 def : InstRW<[GenericDSPShort], (instregex "^EXTPDPV_MM$")>; 719 def : InstRW<[GenericDSPShort], (instregex "^EXTPDP_MM$")>; 720 def : InstRW<[GenericDSPShort], (instregex "^EXTPV_MM$")>; 721 def : InstRW<[GenericDSPShort], (instregex "^EXTP_MM$")>; 722 def : InstRW<[GenericDSPShort], (instregex "^EXTRV_RS_W_MM$")>; 723 def : InstRW<[GenericDSPShort], (instregex "^EXTRV_R_W_MM$")>; 724 def : InstRW<[GenericDSPShort], (instregex "^EXTRV_S_H_MM$")>; 725 def : InstRW<[GenericDSPShort], (instregex "^EXTRV_W_MM$")>; 726 def : InstRW<[GenericDSPShort], (instregex "^EXTR_RS_W_MM$")>; 727 def : InstRW<[GenericDSPShort], (instregex "^EXTR_R_W_MM$")>; 728 def : InstRW<[GenericDSPShort], (instregex "^EXTR_S_H_MM$")>; 729 def : InstRW<[GenericDSPShort], (instregex "^EXTR_W_MM$")>; 730 def : InstRW<[GenericDSPShort], (instregex "^INSV_MM$")>; 731 def : InstRW<[GenericDSPShort], (instregex "^LBUX_MM$")>; 732 def : InstRW<[GenericDSPShort], (instregex "^LHX_MM$")>; 733 def : InstRW<[GenericDSPShort], (instregex "^LWX_MM$")>; 734 def : InstRW<[GenericDSPShort], (instregex "^MADDU_DSP_MM$")>; 735 def : InstRW<[GenericDSPShort], (instregex "^MADD_DSP_MM$")>; 736 def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHL_MM$")>; 737 def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHR_MM$")>; 738 def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL_MM$")>; 739 def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR_MM$")>; 740 def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP_MM$")>; 741 def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP_MM$")>; 742 def : InstRW<[GenericDSPShort], (instregex "^MODSUB_MM$")>; 743 def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MM$")>; 744 def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MMR6$")>; 745 def : InstRW<[GenericDSPShort], (instregex "^MOVN_I_MM$")>; 746 def : InstRW<[GenericDSPShort], (instregex "^MOVZ_I_MM$")>; 747 def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP_MM$")>; 748 def : InstRW<[GenericDSPShort], (instregex "^MSUB_DSP_MM$")>; 749 def : InstRW<[GenericDSPShort], (instregex "^MTHI_DSP_MM$")>; 750 def : InstRW<[GenericDSPShort], (instregex "^MTHLIP_MM$")>; 751 def : InstRW<[GenericDSPShort], (instregex "^MTLO_DSP_MM$")>; 752 def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHL_MM$")>; 753 def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHR_MM$")>; 754 def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBL_MM$")>; 755 def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBR_MM$")>; 756 def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_PH_MM$")>; 757 def : InstRW<[GenericDSPShort], (instregex "^MULSAQ_S_W_PH_MM$")>; 758 def : InstRW<[GenericDSPShort], (instregex "^MULTU_DSP_MM$")>; 759 def : InstRW<[GenericDSPShort], (instregex "^MULT_DSP_MM$")>; 760 def : InstRW<[GenericDSPShort], (instregex "^PACKRL_PH_MM$")>; 761 def : InstRW<[GenericDSPShort], (instregex "^PICK_PH_MM$")>; 762 def : InstRW<[GenericDSPShort], (instregex "^PICK_QB_MM$")>; 763 def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBLA_MM$")>; 764 def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBL_MM$")>; 765 def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBRA_MM$")>; 766 def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBR_MM$")>; 767 def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHL_MM$")>; 768 def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHR_MM$")>; 769 def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBLA_MM$")>; 770 def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBL_MM$")>; 771 def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBRA_MM$")>; 772 def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBR_MM$")>; 773 def : InstRW<[GenericDSPShort], (instregex "^PRECRQU_S_QB_PH_MM$")>; 774 def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_PH_W_MM$")>; 775 def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_QB_PH_MM$")>; 776 def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_RS_PH_W_MM$")>; 777 def : InstRW<[GenericDSPShort], (instregex "^RADDU_W_QB_MM$")>; 778 def : InstRW<[GenericDSPShort], (instregex "^RDDSP_MM$")>; 779 def : InstRW<[GenericDSPShort], (instregex "^REPLV_PH_MM$")>; 780 def : InstRW<[GenericDSPShort], (instregex "^REPLV_QB_MM$")>; 781 def : InstRW<[GenericDSPShort], (instregex "^REPL_PH_MM$")>; 782 def : InstRW<[GenericDSPShort], (instregex "^REPL_QB_MM$")>; 783 def : InstRW<[GenericDSPShort], (instregex "^SHILOV_MM$")>; 784 def : InstRW<[GenericDSPShort], (instregex "^SHILO_MM$")>; 785 def : InstRW<[GenericDSPShort], (instregex "^SHLLV_PH_MM$")>; 786 def : InstRW<[GenericDSPShort], (instregex "^SHLLV_QB_MM$")>; 787 def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_PH_MM$")>; 788 def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_W_MM$")>; 789 def : InstRW<[GenericDSPShort], (instregex "^SHLL_PH_MM$")>; 790 def : InstRW<[GenericDSPShort], (instregex "^SHLL_QB_MM$")>; 791 def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_PH_MM$")>; 792 def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_W_MM$")>; 793 def : InstRW<[GenericDSPShort], (instregex "^SHRAV_PH_MM$")>; 794 def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_PH_MM$")>; 795 def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_W_MM$")>; 796 def : InstRW<[GenericDSPShort], (instregex "^SHRA_PH_MM$")>; 797 def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_PH_MM$")>; 798 def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_W_MM$")>; 799 def : InstRW<[GenericDSPShort], (instregex "^SHRLV_QB_MM$")>; 800 def : InstRW<[GenericDSPShort], (instregex "^SHRL_QB_MM$")>; 801 def : InstRW<[GenericDSPShort], (instregex "^SUBQ_PH_MM$")>; 802 def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_PH_MM$")>; 803 def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_W_MM$")>; 804 def : InstRW<[GenericDSPShort], (instregex "^SUBU_QB_MM$")>; 805 def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_QB_MM$")>; 806 def : InstRW<[GenericDSPShort], (instregex "^WRDSP_MM$")>; 807 808 809 // microMIPS DSP R2 - hasDSP, HasDSPR2, InMicroMips 810 // ================================================ 811 812 def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_QB_MMR2$")>; 813 def : InstRW<[GenericDSPShort], (instregex "^ADDQH_PH_MMR2$")>; 814 def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_PH_MMR2$")>; 815 def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_W_MMR2$")>; 816 def : InstRW<[GenericDSPShort], (instregex "^ADDQH_W_MMR2$")>; 817 def : InstRW<[GenericDSPShort], (instregex "^ADDUH_QB_MMR2$")>; 818 def : InstRW<[GenericDSPShort], (instregex "^ADDUH_R_QB_MMR2$")>; 819 def : InstRW<[GenericDSPShort], (instregex "^ADDU_PH_MMR2$")>; 820 def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_PH_MMR2$")>; 821 def : InstRW<[GenericDSPShort], (instregex "^APPEND_MMR2$")>; 822 def : InstRW<[GenericDSPShort], (instregex "^BALIGN_MMR2$")>; 823 def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_EQ_QB_MMR2$")>; 824 def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LE_QB_MMR2$")>; 825 def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LT_QB_MMR2$")>; 826 def : InstRW<[GenericDSPShort], (instregex "^DPA_W_PH_MMR2$")>; 827 def : InstRW<[GenericDSPShort], (instregex "^DPAQX_SA_W_PH_MMR2$")>; 828 def : InstRW<[GenericDSPShort], (instregex "^DPAQX_S_W_PH_MMR2$")>; 829 def : InstRW<[GenericDSPShort], (instregex "^DPAX_W_PH_MMR2$")>; 830 def : InstRW<[GenericDSPShort], (instregex "^DPS_W_PH_MMR2$")>; 831 def : InstRW<[GenericDSPShort], (instregex "^DPSQX_S_W_PH_MMR2$")>; 832 def : InstRW<[GenericDSPShort], (instregex "^DPSQX_SA_W_PH_MMR2$")>; 833 def : InstRW<[GenericDSPShort], (instregex "^DPSX_W_PH_MMR2$")>; 834 def : InstRW<[GenericDSPShort], (instregex "^MUL_PH_MMR2$")>; 835 def : InstRW<[GenericDSPShort], (instregex "^MUL_S_PH_MMR2$")>; 836 def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_W_MMR2$")>; 837 def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_PH_MMR2$")>; 838 def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_W_MMR2$")>; 839 def : InstRW<[GenericDSPShort], (instregex "^MULSA_W_PH_MMR2$")>; 840 def : InstRW<[GenericDSPShort], (instregex "^PRECR_QB_PH_MMR2$")>; 841 def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_PH_W_MMR2$")>; 842 def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_R_PH_W_MMR2$")>; 843 def : InstRW<[GenericDSPShort], (instregex "^PREPEND_MMR2$")>; 844 def : InstRW<[GenericDSPShort], (instregex "^SHRA_QB_MMR2$")>; 845 def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_QB_MMR2$")>; 846 def : InstRW<[GenericDSPShort], (instregex "^SHRAV_QB_MMR2$")>; 847 def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_QB_MMR2$")>; 848 def : InstRW<[GenericDSPShort], (instregex "^SHRL_PH_MMR2$")>; 849 def : InstRW<[GenericDSPShort], (instregex "^SHRLV_PH_MMR2$")>; 850 def : InstRW<[GenericDSPShort], (instregex "^SUBQH_PH_MMR2$")>; 851 def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_PH_MMR2$")>; 852 def : InstRW<[GenericDSPShort], (instregex "^SUBQH_W_MMR2$")>; 853 def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_W_MMR2$")>; 854 def : InstRW<[GenericDSPShort], (instregex "^SUBU_PH_MMR2$")>; 855 def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_PH_MMR2$")>; 856 def : InstRW<[GenericDSPShort], (instregex "^SUBUH_QB_MMR2$")>; 857 def : InstRW<[GenericDSPShort], (instregex "^SUBUH_R_QB_MMR2$")>; 858 859 // microMIPS DSP R3 - hasDSP, hasDSPR2, hasDSPR3, InMicroMips 860 // ========================================================== 861 862 def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32C_MMR3$")>; 863 864 // MIPS MSA ASE - hasMSA 865 // ===================== 866 867 def GenericWriteMSAShortLogic : SchedWriteRes<[GenericIssueFPUS]>; 868 def GenericWriteMSAShortInt : SchedWriteRes<[GenericIssueFPUS]> { 869 let Latency = 2; 870 } 871 def GenericWriteMoveOtherUnitsToFPU : SchedWriteRes<[GenericIssueFPUS]>; 872 def GenericWriteMSAOther3 : SchedWriteRes<[GenericIssueFPUS]> { 873 let Latency = 3; 874 } 875 def GenericWriteMSALongInt : SchedWriteRes<[GenericIssueFPUS]> { 876 let Latency = 5; 877 } 878 def GenericWriteFPUDivI : SchedWriteRes<[GenericFPQ]> { 879 let Latency = 33; 880 let ResourceCycles = [ 33 ]; 881 } 882 883 // FPUS is also used in moves from floating point and MSA registers to general 884 // purpose registers. 885 def GenericWriteMoveFPUSToOtherUnits : SchedWriteRes<[GenericIssueFPUS]> { 886 let Latency = 0; 887 } 888 889 // FPUL is also used in moves from floating point and MSA registers to general 890 // purpose registers. 891 def GenericWriteMoveFPULToOtherUnits : SchedWriteRes<[GenericIssueFPUL]>; 892 893 894 // adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd], 895 // aver?_[us].[bhwd] 896 def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADD_A_[BHWD]$")>; 897 def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADDS_[ASU]_[BHWD]$")>; 898 899 // TODO: ADDVI_[BHW] might be 1 cycle latency rather than 2. Need to confirm it. 900 // add.[bhwd], addvi.[bhwd], asub_[us].[bhwd], ave.[bhwd], aver.[bhwd] 901 def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADDVI?_[BHWD]$")>; 902 def : InstRW<[GenericWriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>; 903 def : InstRW<[GenericWriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>; 904 905 // and.v, andi.b, move.v, ldi.[bhwd], xor.v, nor.v, xori.b, nori.b 906 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^MOVE_V$")>; 907 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>; 908 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>; 909 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; 910 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; 911 912 // vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd], 913 // bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b 914 def : InstRW<[GenericWriteMSAShortInt], (instregex "^VSHF_[BHWD]$")>; 915 def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BINSL|BINSLI)_[BHWD]$")>; 916 def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BINSR|BINSRI)_[BHWD]$")>; 917 def : InstRW<[GenericWriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>; 918 def : InstRW<[GenericWriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>; 919 def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>; 920 def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>; 921 def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>; 922 def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; 923 def : InstRW<[GenericWriteMSAShortInt], (instregex "^BMN*Z.*$")>; 924 925 // pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] 926 def : InstRW<[GenericWriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; 927 def : InstRW<[GenericWriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; 928 929 // bnz.[bhwdv], cfcmsa, ctcmsa 930 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(BNZ|BZ)_[BHWDV]$")>; 931 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^C(F|T)CMSA$")>; 932 933 // shf.[bhw], fill[bhwd], splat?.[bhwd] 934 def : InstRW<[GenericWriteMSAShortInt], (instregex "^SHF_[BHW]$")>; 935 def : InstRW<[GenericWriteMSAShortInt], (instregex "^FILL_[BHWD]$")>; 936 def : InstRW<[GenericWriteMSAShortInt], (instregex "^(SPLAT|SPLATI)_[BHWD]$")>; 937 938 // pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] 939 def : InstRW<[GenericWriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; 940 def : InstRW<[GenericWriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; 941 942 // fexp2_w, fexp2_d 943 def : InstRW<[GenericWriteFPUS], (instregex "^FEXP2_(W|D)$")>; 944 945 // compare, converts, round to int, floating point truncate. 946 def : InstRW<[GenericWriteFPUS], (instregex "^(CLT|CLTI)_(S|U)_[BHWD]$")>; 947 def : InstRW<[GenericWriteFPUS], (instregex "^(CLE|CLEI)_(S|U)_[BHWD]$")>; 948 def : InstRW<[GenericWriteFPUS], (instregex "^(CEQ|CEQI)_[BHWD]$")>; 949 def : InstRW<[GenericWriteFPUS], (instregex "^CMP_UN_(S|D)$")>; 950 def : InstRW<[GenericWriteFPUS], (instregex "^CMP_UEQ_(S|D)$")>; 951 def : InstRW<[GenericWriteFPUS], (instregex "^CMP_EQ_(S|D)$")>; 952 def : InstRW<[GenericWriteFPUS], (instregex "^CMP_LT_(S|D)$")>; 953 def : InstRW<[GenericWriteFPUS], (instregex "^CMP_ULT_(S|D)$")>; 954 def : InstRW<[GenericWriteFPUS], (instregex "^CMP_LE_(S|D)$")>; 955 def : InstRW<[GenericWriteFPUS], (instregex "^CMP_ULE_(S|D)$")>; 956 def : InstRW<[GenericWriteFPUS], (instregex "^FS(AF|EQ|LT|LE|NE|OR)_(W|D)$")>; 957 def : InstRW<[GenericWriteFPUS], (instregex "^FSUEQ_(W|D)$")>; 958 def : InstRW<[GenericWriteFPUS], (instregex "^FSULE_(W|D)$")>; 959 def : InstRW<[GenericWriteFPUS], (instregex "^FSULT_(W|D)$")>; 960 def : InstRW<[GenericWriteFPUS], (instregex "^FSUNE_(W|D)$")>; 961 def : InstRW<[GenericWriteFPUS], (instregex "^FSUN_(W|D)$")>; 962 def : InstRW<[GenericWriteFPUS], (instregex "^FCAF_(W|D)$")>; 963 def : InstRW<[GenericWriteFPUS], (instregex "^FCEQ_(W|D)$")>; 964 def : InstRW<[GenericWriteFPUS], (instregex "^FCLE_(W|D)$")>; 965 def : InstRW<[GenericWriteFPUS], (instregex "^FCLT_(W|D)$")>; 966 def : InstRW<[GenericWriteFPUS], (instregex "^FCNE_(W|D)$")>; 967 def : InstRW<[GenericWriteFPUS], (instregex "^FCOR_(W|D)$")>; 968 def : InstRW<[GenericWriteFPUS], (instregex "^FCUEQ_(W|D)$")>; 969 def : InstRW<[GenericWriteFPUS], (instregex "^FCULE_(W|D)$")>; 970 def : InstRW<[GenericWriteFPUS], (instregex "^FCULT_(W|D)$")>; 971 def : InstRW<[GenericWriteFPUS], (instregex "^FCUNE_(W|D)$")>; 972 def : InstRW<[GenericWriteFPUS], (instregex "^FCUN_(W|D)$")>; 973 def : InstRW<[GenericWriteFPUS], (instregex "^FABS_(W|D)$")>; 974 def : InstRW<[GenericWriteFPUS], (instregex "^FFINT_(U|S)_(W|D)$")>; 975 def : InstRW<[GenericWriteFPUS], (instregex "^FFQL_(W|D)$")>; 976 def : InstRW<[GenericWriteFPUS], (instregex "^FFQR_(W|D)$")>; 977 def : InstRW<[GenericWriteFPUS], (instregex "^FTINT_(U|S)_(W|D)$")>; 978 def : InstRW<[GenericWriteFPUS], (instregex "^FRINT_(W|D)$")>; 979 def : InstRW<[GenericWriteFPUS], (instregex "^FTQ_(H|W)$")>; 980 def : InstRW<[GenericWriteFPUS], (instregex "^FTRUNC_(U|S)_(W|D)$")>; 981 982 // fexdo.[hw], fexupl.[wd], fexupr.[wd] 983 def : InstRW<[GenericWriteFPUS], (instregex "^FEXDO_(H|W)$")>; 984 def : InstRW<[GenericWriteFPUS], (instregex "^FEXUPL_(W|D)$")>; 985 def : InstRW<[GenericWriteFPUS], (instregex "^FEXUPR_(W|D)$")>; 986 987 // fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd] 988 def : InstRW<[GenericWriteFPUS], (instregex "^FCLASS_(W|D)$")>; 989 def : InstRW<[GenericWriteFPUS], (instregex "^FMAX_A_(W|D)$")>; 990 def : InstRW<[GenericWriteFPUS], (instregex "^FMAX_(W|D)$")>; 991 def : InstRW<[GenericWriteFPUS], (instregex "^FMIN_A_(W|D)$")>; 992 def : InstRW<[GenericWriteFPUS], (instregex "^FMIN_(W|D)$")>; 993 def : InstRW<[GenericWriteFPUS], (instregex "^FLOG2_(W|D)$")>; 994 995 // interleave right/left, interleave even/odd, insert 996 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVR|ILVL)_[BHWD]$")>; 997 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>; 998 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>; 999 1000 // subs_?.[bhwd], subsus_?.[bhwd], subsuu_?.[bhwd], subvi.[bhwd], subv.[bhwd], 1001 def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBS_(S|U)_[BHWD]$")>; 1002 def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBSUS_(S|U)_[BHWD]$")>; 1003 def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBSUU_(S|U)_[BHWD]$")>; 1004 def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBVI_[BHWD]$")>; 1005 def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBV_[BHWD]$")>; 1006 1007 // mod_[su].[bhwd], div_[su].[bhwd] 1008 def : InstRW<[GenericWriteFPUDivI], (instregex "^MOD_(S|U)_[BHWD]$")>; 1009 def : InstRW<[GenericWriteFPUDivI], (instregex "^DIV_(S|U)_[BHWD]$")>; 1010 1011 // hadd_[su].[bhwd], hsub_[su].[bhwd], max_[sua].[bhwd], min_[sua].[bhwd], 1012 // maxi_[su].[bhwd], mini_[su].[bhwd], sra?.[bhwd], srar?.[bhwd], srlr.[bhwd], 1013 // sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd], 1014 // insve.[bhwd] 1015 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^HADD_(S|U)_[BHWD]$")>; 1016 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^HSUB_(S|U)_[BHWD]$")>; 1017 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_S_[BHWD]$")>; 1018 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_U_[BHWD]$")>; 1019 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_A_[BHWD]$")>; 1020 def : InstRW<[GenericWriteMSAShortLogic], 1021 (instregex "^(MAXI|MINI)_(S|U)_[BHWD]$")>; 1022 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRA|SRAI)_[BHWD]$")>; 1023 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>; 1024 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRAR|SRARI)_[BHWD]$")>; 1025 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRLR|SRLRI)_[BHWD]$")>; 1026 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>; 1027 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(PCKEV|PCKOD)_[BHWD]$")>; 1028 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>; 1029 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>; 1030 1031 // dpadd_?.[bhwd], dpsub_?.[bhwd], dotp_?.[bhwd], msubv.[bhwd], maddv.[bhwd] 1032 // mulv.[bhwd]. 1033 def : InstRW<[GenericWriteMSALongInt], (instregex "^DPADD_(S|U)_[HWD]$")>; 1034 def : InstRW<[GenericWriteMSALongInt], (instregex "^DPSUB_(S|U)_[HWD]$")>; 1035 def : InstRW<[GenericWriteMSALongInt], (instregex "^DOTP_(S|U)_[HWD]$")>; 1036 def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUBV_[BHWD]$")>; 1037 def : InstRW<[GenericWriteMSALongInt], (instregex "^MADDV_[BHWD]$")>; 1038 def : InstRW<[GenericWriteMSALongInt], (instregex "^MULV_[BHWD]$")>; 1039 1040 // madd?.q.[hw], msub?.q.[hw], mul?.q.[hw] 1041 def : InstRW<[GenericWriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>; 1042 def : InstRW<[GenericWriteMSALongInt], (instregex "^MADD_Q_[HW]$")>; 1043 def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>; 1044 def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>; 1045 def : InstRW<[GenericWriteMSALongInt], (instregex "^MULR_Q_[HW]$")>; 1046 def : InstRW<[GenericWriteMSALongInt], (instregex "^MUL_Q_[HW]$")>; 1047 1048 // fadd.[dw], fmadd.[dw], fmul.[dw], frcp.[dw], frsqrt.[dw], fsqrt.[dw] 1049 // fsub.[dw], fdiv.[dw] 1050 def : InstRW<[GenericWriteFPUL], (instregex "^FADD_[DW]$")>; 1051 def : InstRW<[GenericWriteFPUL], (instregex "^FMADD_[DW]$")>; 1052 def : InstRW<[GenericWriteFPUL], (instregex "^FMSUB_[DW]$")>; 1053 def : InstRW<[GenericWriteFPUL], (instregex "^FMUL_[DW]$")>; 1054 def : InstRW<[GenericWriteFPUL], (instregex "^FRCP_[DW]$")>; 1055 def : InstRW<[GenericWriteFPUL], (instregex "^FRSQRT_[DW]$")>; 1056 def : InstRW<[GenericWriteFPUL], (instregex "^FSQRT_[DW]$")>; 1057 def : InstRW<[GenericWriteFPUL], (instregex "^FSUB_[DW]$")>; 1058 def : InstRW<[GenericWriteFPUL], (instregex "^FDIV_[DW]$")>; 1059 1060 // copy.[su]_[bhwd] 1061 def : InstRW<[GenericWriteFPUMoveGPRFPU], (instregex "^COPY_U_[BHW]$")>; 1062 def : InstRW<[GenericWriteFPUMoveGPRFPU], (instregex "^COPY_S_[BHWD]$")>; 1063 1064 def : InstRW<[GenericWriteFPUStore], (instregex "^ST_[BHWD]$")>; 1065 def : InstRW<[GenericWriteFPULoad], (instregex "^LD_[BHWD]$")>; 1066 } 1067
