Home | History | Annotate | Download | only in NVPTX 
      1 //===-- NVPTXTargetTransformInfo.h - NVPTX specific TTI ---------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 /// \file
     10 /// This file a TargetTransformInfo::Concept conforming object specific to the
     11 /// NVPTX target machine. It uses the target's detailed information to
     12 /// provide more precise answers to certain TTI queries, while letting the
     13 /// target independent and default TTI implementations handle the rest.
     14 ///
     15 //===----------------------------------------------------------------------===//
     16 
     17 #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
     18 #define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETTRANSFORMINFO_H
     19 
     20 #include "NVPTX.h"
     21 #include "NVPTXTargetMachine.h"
     22 #include "llvm/Analysis/TargetTransformInfo.h"
     23 #include "llvm/CodeGen/BasicTTIImpl.h"
     24 #include "llvm/CodeGen/TargetLowering.h"
     25 
     26 namespace llvm {
     27 
     28 class NVPTXTTIImpl : public BasicTTIImplBase<NVPTXTTIImpl> {
     29   typedef BasicTTIImplBase<NVPTXTTIImpl> BaseT;
     30   typedef TargetTransformInfo TTI;
     31   friend BaseT;
     32 
     33   const NVPTXSubtarget *ST;
     34   const NVPTXTargetLowering *TLI;
     35 
     36   const NVPTXSubtarget *getST() const { return ST; };
     37   const NVPTXTargetLowering *getTLI() const { return TLI; };
     38 
     39 public:
     40   explicit NVPTXTTIImpl(const NVPTXTargetMachine *TM, const Function &F)
     41       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl()),
     42         TLI(ST->getTargetLowering()) {}
     43 
     44   bool hasBranchDivergence() { return true; }
     45 
     46   bool isSourceOfDivergence(const Value *V);
     47 
     48   unsigned getFlatAddressSpace() const {
     49     return AddressSpace::ADDRESS_SPACE_GENERIC;
     50   }
     51 
     52   // NVPTX has infinite registers of all kinds, but the actual machine doesn't.
     53   // We conservatively return 1 here which is just enough to enable the
     54   // vectorizers but disables heuristics based on the number of registers.
     55   // FIXME: Return a more reasonable number, while keeping an eye on
     56   // LoopVectorizer's unrolling heuristics.
     57   unsigned getNumberOfRegisters(bool Vector) const { return 1; }
     58 
     59   // Only <2 x half> should be vectorized, so always return 32 for the vector
     60   // register size.
     61   unsigned getRegisterBitWidth(bool Vector) const { return 32; }
     62   unsigned getMinVectorRegisterBitWidth() const { return 32; }
     63 
     64   // We don't want to prevent inlining because of target-cpu and -features
     65   // attributes that were added to newer versions of LLVM/Clang: There are
     66   // no incompatible functions in PTX, ptxas will throw errors in such cases.
     67   bool areInlineCompatible(const Function *Caller,
     68                            const Function *Callee) const {
     69     return true;
     70   }
     71 
     72   // Increase the inlining cost threshold by a factor of 5, reflecting that
     73   // calls are particularly expensive in NVPTX.
     74   unsigned getInliningThresholdMultiplier() { return 5; }
     75 
     76   int getArithmeticInstrCost(
     77       unsigned Opcode, Type *Ty,
     78       TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
     79       TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
     80       TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
     81       TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
     82       ArrayRef<const Value *> Args = ArrayRef<const Value *>());
     83 
     84   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
     85                                TTI::UnrollingPreferences &UP);
     86   bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) {
     87     // Volatile loads/stores are only supported for shared and global address
     88     // spaces, or for generic AS that maps to them.
     89     if (!(AddrSpace == llvm::ADDRESS_SPACE_GENERIC ||
     90           AddrSpace == llvm::ADDRESS_SPACE_GLOBAL ||
     91           AddrSpace == llvm::ADDRESS_SPACE_SHARED))
     92       return false;
     93 
     94     switch(I->getOpcode()){
     95     default:
     96       return false;
     97     case Instruction::Load:
     98     case Instruction::Store:
     99       return true;
    100     }
    101   }
    102 };
    103 
    104 } // end namespace llvm
    105 
    106 #endif
    107