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      1 //===-- RISCVCallingConv.td - Calling Conventions RISCV ----*- tablegen -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This describes the calling conventions for the RISCV architecture.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 // The RISC-V calling convention is handled with custom code in
     15 // RISCVISelLowering.cpp (CC_RISCV).
     16 
     17 def CSR : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
     18 
     19 // Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
     20 def CSR_NoRegs : CalleeSavedRegs<(add)>;
     21 
     22 // Interrupt handler needs to save/restore all registers that are used,
     23 // both Caller and Callee saved registers.
     24 def CSR_Interrupt : CalleeSavedRegs<(add X1,
     25     (sequence "X%u", 3, 9),
     26     (sequence "X%u", 10, 11),
     27     (sequence "X%u", 12, 17),
     28     (sequence "X%u", 18, 27),
     29     (sequence "X%u", 28, 31))>;
     30 
     31 // Same as CSR_Interrupt, but including all 32-bit FP registers.
     32 def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add X1,
     33     (sequence "X%u", 3, 9),
     34     (sequence "X%u", 10, 11),
     35     (sequence "X%u", 12, 17),
     36     (sequence "X%u", 18, 27),
     37     (sequence "X%u", 28, 31),
     38     (sequence "F%u_32", 0, 7),
     39     (sequence "F%u_32", 10, 11),
     40     (sequence "F%u_32", 12, 17),
     41     (sequence "F%u_32", 28, 31),
     42     (sequence "F%u_32", 8, 9),
     43     (sequence "F%u_32", 18, 27))>;
     44 
     45 // Same as CSR_Interrupt, but including all 64-bit FP registers.
     46 def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add X1,
     47     (sequence "X%u", 3, 9),
     48     (sequence "X%u", 10, 11),
     49     (sequence "X%u", 12, 17),
     50     (sequence "X%u", 18, 27),
     51     (sequence "X%u", 28, 31),
     52     (sequence "F%u_64", 0, 7),
     53     (sequence "F%u_64", 10, 11),
     54     (sequence "F%u_64", 12, 17),
     55     (sequence "F%u_64", 28, 31),
     56     (sequence "F%u_64", 8, 9),
     57     (sequence "F%u_64", 18, 27))>;
     58