1 //===-- RISCVInstrFormatsC.td - RISCV C Instruction Formats --*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the RISC-V C extension instruction formats. 11 // 12 //===----------------------------------------------------------------------===// 13 14 class RVInst16<dag outs, dag ins, string opcodestr, string argstr, 15 list<dag> pattern, InstFormat format> 16 : Instruction { 17 field bits<16> Inst; 18 // SoftFail is a field the disassembler can use to provide a way for 19 // instructions to not match without killing the whole decode process. It is 20 // mainly used for ARM, but Tablegen expects this field to exist or it fails 21 // to build the decode table. 22 field bits<16> SoftFail = 0; 23 let Size = 2; 24 25 bits<2> Opcode = 0; 26 27 let Namespace = "RISCV"; 28 29 dag OutOperandList = outs; 30 dag InOperandList = ins; 31 let AsmString = opcodestr # "\t" # argstr; 32 let Pattern = pattern; 33 34 let TSFlags{4-0} = format.Value; 35 } 36 37 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins, 38 string opcodestr, string argstr> 39 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCR> { 40 bits<5> rs1; 41 bits<5> rs2; 42 43 let Inst{15-12} = funct4; 44 let Inst{11-7} = rs1; 45 let Inst{6-2} = rs2; 46 let Inst{1-0} = opcode; 47 } 48 49 // The immediate value encoding differs for each instruction, so each subclass 50 // is responsible for setting the appropriate bits in the Inst field. 51 // The bits Inst{6-2} must be set for each instruction. 52 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 53 string opcodestr, string argstr> 54 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCI> { 55 bits<10> imm; 56 bits<5> rd; 57 bits<5> rs1; 58 59 let Inst{15-13} = funct3; 60 let Inst{12} = imm{5}; 61 let Inst{11-7} = rd; 62 let Inst{1-0} = opcode; 63 } 64 65 // The immediate value encoding differs for each instruction, so each subclass 66 // is responsible for setting the appropriate bits in the Inst field. 67 // The bits Inst{12-7} must be set for each instruction. 68 class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 69 string opcodestr, string argstr> 70 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSS> { 71 bits<10> imm; 72 bits<5> rs2; 73 bits<5> rs1; 74 75 let Inst{15-13} = funct3; 76 let Inst{6-2} = rs2; 77 let Inst{1-0} = opcode; 78 } 79 80 class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 81 string opcodestr, string argstr> 82 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCIW> { 83 bits<10> imm; 84 bits<3> rd; 85 86 let Inst{15-13} = funct3; 87 let Inst{4-2} = rd; 88 let Inst{1-0} = opcode; 89 } 90 91 // The immediate value encoding differs for each instruction, so each subclass 92 // is responsible for setting the appropriate bits in the Inst field. 93 // The bits Inst{12-10} and Inst{6-5} must be set for each instruction. 94 class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 95 string opcodestr, string argstr> 96 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCL> { 97 bits<3> rd; 98 bits<3> rs1; 99 100 let Inst{15-13} = funct3; 101 let Inst{9-7} = rs1; 102 let Inst{4-2} = rd; 103 let Inst{1-0} = opcode; 104 } 105 106 // The immediate value encoding differs for each instruction, so each subclass 107 // is responsible for setting the appropriate bits in the Inst field. 108 // The bits Inst{12-10} and Inst{6-5} must be set for each instruction. 109 class RVInst16CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 110 string opcodestr, string argstr> 111 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCS> { 112 bits<3> rs2; 113 bits<3> rs1; 114 115 let Inst{15-13} = funct3; 116 let Inst{9-7} = rs1; 117 let Inst{4-2} = rs2; 118 let Inst{1-0} = opcode; 119 } 120 121 class RVInst16CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 122 string opcodestr, string argstr> 123 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCB> { 124 bits<9> imm; 125 bits<3> rs1; 126 127 let Inst{15-13} = funct3; 128 let Inst{9-7} = rs1; 129 let Inst{1-0} = opcode; 130 } 131 132 class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 133 string opcodestr, string argstr> 134 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCJ> { 135 bits<11> offset; 136 137 let Inst{15-13} = funct3; 138 let Inst{12} = offset{10}; 139 let Inst{11} = offset{3}; 140 let Inst{10-9} = offset{8-7}; 141 let Inst{8} = offset{9}; 142 let Inst{7} = offset{5}; 143 let Inst{6} = offset{6}; 144 let Inst{5-3} = offset{2-0}; 145 let Inst{2} = offset{4}; 146 let Inst{1-0} = opcode; 147 } 148
