1 //===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the RISC-V instructions from the standard 'D', 11 // Double-Precision Floating-Point instruction set extension. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // RISC-V specific DAG Nodes. 17 //===----------------------------------------------------------------------===// 18 19 def SDT_RISCVBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 20 SDTCisVT<1, i32>, 21 SDTCisSameAs<1, 2>]>; 22 def SDT_RISCVSplitF64 : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, 23 SDTCisVT<1, i32>, 24 SDTCisVT<2, f64>]>; 25 26 def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>; 27 def RISCVSplitF64 : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>; 28 29 //===----------------------------------------------------------------------===// 30 // Instruction Class Templates 31 //===----------------------------------------------------------------------===// 32 33 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 34 class FPFMAD_rrr_frm<RISCVOpcode opcode, string opcodestr> 35 : RVInstR4<0b01, opcode, (outs FPR64:$rd), 36 (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3), 37 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">; 38 39 class FPFMADDynFrmAlias<FPFMAD_rrr_frm Inst, string OpcodeStr> 40 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3", 41 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; 42 43 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 44 class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr> 45 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd), 46 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">; 47 48 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 49 class FPALUD_rr_frm<bits<7> funct7, string opcodestr> 50 : RVInstRFrm<funct7, OPC_OP_FP, (outs FPR64:$rd), 51 (ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr, 52 "$rd, $rs1, $rs2, $funct3">; 53 54 class FPALUDDynFrmAlias<FPALUD_rr_frm Inst, string OpcodeStr> 55 : InstAlias<OpcodeStr#" $rd, $rs1, $rs2", 56 (Inst FPR64:$rd, FPR64:$rs1, FPR64:$rs2, 0b111)>; 57 58 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 59 class FPCmpD_rr<bits<3> funct3, string opcodestr> 60 : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd), 61 (ins FPR64:$rs1, FPR64:$rs2), opcodestr, "$rd, $rs1, $rs2">; 62 63 //===----------------------------------------------------------------------===// 64 // Instructions 65 //===----------------------------------------------------------------------===// 66 67 let Predicates = [HasStdExtD] in { 68 69 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in 70 def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd), 71 (ins GPR:$rs1, simm12:$imm12), 72 "fld", "$rd, ${imm12}(${rs1})">; 73 74 // Operands for stores are in the order srcreg, base, offset rather than 75 // reflecting the order these fields are specified in the instruction 76 // encoding. 77 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 78 def FSD : RVInstS<0b011, OPC_STORE_FP, (outs), 79 (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12), 80 "fsd", "$rs2, ${imm12}(${rs1})">; 81 82 def FMADD_D : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">; 83 def : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">; 84 def FMSUB_D : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">; 85 def : FPFMADDynFrmAlias<FMSUB_D, "fmsub.d">; 86 def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">; 87 def : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">; 88 def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">; 89 def : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">; 90 91 def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">; 92 def : FPALUDDynFrmAlias<FADD_D, "fadd.d">; 93 def FSUB_D : FPALUD_rr_frm<0b0000101, "fsub.d">; 94 def : FPALUDDynFrmAlias<FSUB_D, "fsub.d">; 95 def FMUL_D : FPALUD_rr_frm<0b0001001, "fmul.d">; 96 def : FPALUDDynFrmAlias<FMUL_D, "fmul.d">; 97 def FDIV_D : FPALUD_rr_frm<0b0001101, "fdiv.d">; 98 def : FPALUDDynFrmAlias<FDIV_D, "fdiv.d">; 99 100 def FSQRT_D : FPUnaryOp_r_frm<0b0101101, FPR64, FPR64, "fsqrt.d"> { 101 let rs2 = 0b00000; 102 } 103 def : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>; 104 105 def FSGNJ_D : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">; 106 def FSGNJN_D : FPALUD_rr<0b0010001, 0b001, "fsgnjn.d">; 107 def FSGNJX_D : FPALUD_rr<0b0010001, 0b010, "fsgnjx.d">; 108 def FMIN_D : FPALUD_rr<0b0010101, 0b000, "fmin.d">; 109 def FMAX_D : FPALUD_rr<0b0010101, 0b001, "fmax.d">; 110 111 def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, FPR32, FPR64, "fcvt.s.d"> { 112 let rs2 = 0b00001; 113 } 114 def : FPUnaryOpDynFrmAlias<FCVT_S_D, "fcvt.s.d", FPR32, FPR64>; 115 116 def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s"> { 117 let rs2 = 0b00000; 118 } 119 120 def FEQ_D : FPCmpD_rr<0b010, "feq.d">; 121 def FLT_D : FPCmpD_rr<0b001, "flt.d">; 122 def FLE_D : FPCmpD_rr<0b000, "fle.d">; 123 124 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b001, GPR, FPR64, "fclass.d"> { 125 let rs2 = 0b00000; 126 } 127 128 def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.w.d"> { 129 let rs2 = 0b00000; 130 } 131 def : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>; 132 133 def FCVT_WU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.wu.d"> { 134 let rs2 = 0b00001; 135 } 136 def : FPUnaryOpDynFrmAlias<FCVT_WU_D, "fcvt.wu.d", GPR, FPR64>; 137 138 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w"> { 139 let rs2 = 0b00000; 140 } 141 142 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu"> { 143 let rs2 = 0b00001; 144 } 145 } // Predicates = [HasStdExtD] 146 147 let Predicates = [HasStdExtD, IsRV64] in { 148 def FCVT_L_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.l.d"> { 149 let rs2 = 0b00010; 150 } 151 def : FPUnaryOpDynFrmAlias<FCVT_L_D, "fcvt.l.d", GPR, FPR64>; 152 153 def FCVT_LU_D : FPUnaryOp_r_frm<0b1100001, GPR, FPR64, "fcvt.lu.d"> { 154 let rs2 = 0b00011; 155 } 156 def : FPUnaryOpDynFrmAlias<FCVT_LU_D, "fcvt.lu.d", GPR, FPR64>; 157 158 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d"> { 159 let rs2 = 0b00000; 160 } 161 162 def FCVT_D_L : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.l"> { 163 let rs2 = 0b00010; 164 } 165 def : FPUnaryOpDynFrmAlias<FCVT_D_L, "fcvt.d.l", FPR64, GPR>; 166 167 def FCVT_D_LU : FPUnaryOp_r_frm<0b1101001, FPR64, GPR, "fcvt.d.lu"> { 168 let rs2 = 0b00011; 169 } 170 def : FPUnaryOpDynFrmAlias<FCVT_D_LU, "fcvt.d.lu", FPR64, GPR>; 171 172 def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x"> { 173 let rs2 = 0b00000; 174 } 175 } // Predicates = [HasStdExtD, IsRV64] 176 177 //===----------------------------------------------------------------------===// 178 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20) 179 //===----------------------------------------------------------------------===// 180 181 let Predicates = [HasStdExtD] in { 182 // TODO fld 183 // TODO fsd 184 185 def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 186 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 187 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; 188 189 // fgt.d/fge.d are recognised by the GNU assembler but the canonical 190 // flt.d/fle.d forms will always be printed. Therefore, set a zero weight. 191 def : InstAlias<"fgt.d $rd, $rs, $rt", 192 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 193 def : InstAlias<"fge.d $rd, $rs, $rt", 194 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; 195 } // Predicates = [HasStdExtD] 196 197 //===----------------------------------------------------------------------===// 198 // Pseudo-instructions and codegen patterns 199 //===----------------------------------------------------------------------===// 200 201 class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst> 202 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>; 203 204 class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst> 205 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>; 206 207 let Predicates = [HasStdExtD] in { 208 209 /// Float conversion operations 210 211 // f64 -> f32, f32 -> f64 212 def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>; 213 def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>; 214 215 // FP->[u]int. Round-to-zero must be used 216 def : Pat<(fp_to_sint FPR64:$rs1), (FCVT_W_D FPR64:$rs1, 0b001)>; 217 def : Pat<(fp_to_uint FPR64:$rs1), (FCVT_WU_D FPR64:$rs1, 0b001)>; 218 219 // [u]int->fp 220 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_D_W GPR:$rs1)>; 221 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_D_WU GPR:$rs1)>; 222 223 /// Float arithmetic operations 224 225 def : PatFpr64Fpr64DynFrm<fadd, FADD_D>; 226 def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>; 227 def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>; 228 def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>; 229 230 def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>; 231 232 def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>; 233 def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>; 234 235 def : PatFpr64Fpr64<fcopysign, FSGNJ_D>; 236 def : Pat<(fcopysign FPR64:$rs1, (fneg FPR64:$rs2)), (FSGNJN_D $rs1, $rs2)>; 237 238 // The RISC-V 2.2 user-level ISA spec defines fmin and fmax as returning the 239 // canonical NaN when giving a signaling NaN. This doesn't match the LLVM 240 // behaviour (see https://bugs.llvm.org/show_bug.cgi?id=27363). However, the 241 // draft 2.3 ISA spec changes the definition of fmin and fmax in a way that 242 // matches LLVM's fminnum and fmaxnum 243 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. 244 def : PatFpr64Fpr64<fminnum, FMIN_D>; 245 def : PatFpr64Fpr64<fmaxnum, FMAX_D>; 246 247 /// Setcc 248 249 def : PatFpr64Fpr64<seteq, FEQ_D>; 250 def : PatFpr64Fpr64<setoeq, FEQ_D>; 251 def : PatFpr64Fpr64<setlt, FLT_D>; 252 def : PatFpr64Fpr64<setolt, FLT_D>; 253 def : PatFpr64Fpr64<setle, FLE_D>; 254 def : PatFpr64Fpr64<setole, FLE_D>; 255 256 // Define pattern expansions for setcc operations which aren't directly 257 // handled by a RISC-V instruction and aren't expanded in the SelectionDAG 258 // Legalizer. 259 260 def : Pat<(setuo FPR64:$rs1, FPR64:$rs2), 261 (SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1), 262 (FEQ_D FPR64:$rs2, FPR64:$rs2)), 263 1)>; 264 265 def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>; 266 267 /// Loads 268 269 defm : LdPat<load, FLD>; 270 271 /// Stores 272 273 defm : StPat<store, FSD, FPR64>; 274 275 /// Pseudo-instructions needed for the soft-float ABI with RV32D 276 277 // Moves two GPRs to an FPR. 278 let usesCustomInserter = 1 in 279 def BuildPairF64Pseudo 280 : Pseudo<(outs FPR64:$dst), (ins GPR:$src1, GPR:$src2), 281 [(set FPR64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>; 282 283 // Moves an FPR to two GPRs. 284 let usesCustomInserter = 1 in 285 def SplitF64Pseudo 286 : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins FPR64:$src), 287 [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 FPR64:$src))]>; 288 289 } // Predicates = [HasStdExtD] 290
