1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Sparc instructions in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Instruction format superclass 16 //===----------------------------------------------------------------------===// 17 18 include "SparcInstrFormats.td" 19 20 //===----------------------------------------------------------------------===// 21 // Feature predicates. 22 //===----------------------------------------------------------------------===// 23 24 // True when generating 32-bit code. 25 def Is32Bit : Predicate<"!Subtarget->is64Bit()">; 26 27 // True when generating 64-bit code. This also implies HasV9. 28 def Is64Bit : Predicate<"Subtarget->is64Bit()">; 29 30 def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">, 31 AssemblerPredicate<"FeatureSoftMulDiv">; 32 33 // HasV9 - This predicate is true when the target processor supports V9 34 // instructions. Note that the machine may be running in 32-bit mode. 35 def HasV9 : Predicate<"Subtarget->isV9()">, 36 AssemblerPredicate<"FeatureV9">; 37 38 // HasNoV9 - This predicate is true when the target doesn't have V9 39 // instructions. Use of this is just a hack for the isel not having proper 40 // costs for V8 instructions that are more expensive than their V9 ones. 41 def HasNoV9 : Predicate<"!Subtarget->isV9()">; 42 43 // HasVIS - This is true when the target processor has VIS extensions. 44 def HasVIS : Predicate<"Subtarget->isVIS()">, 45 AssemblerPredicate<"FeatureVIS">; 46 def HasVIS2 : Predicate<"Subtarget->isVIS2()">, 47 AssemblerPredicate<"FeatureVIS2">; 48 def HasVIS3 : Predicate<"Subtarget->isVIS3()">, 49 AssemblerPredicate<"FeatureVIS3">; 50 51 // HasHardQuad - This is true when the target processor supports quad floating 52 // point instructions. 53 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; 54 55 // HasLeonCASA - This is true when the target processor supports the CASA 56 // instruction 57 def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">; 58 59 // HasUMAC_SMAC - This is true when the target processor supports the 60 // UMAC and SMAC instructions 61 def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">; 62 63 def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">; 64 def HasFMULS : Predicate<"!Subtarget->hasNoFMULS()">; 65 def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">; 66 67 // UseDeprecatedInsts - This predicate is true when the target processor is a 68 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough 69 // to use when appropriate. In either of these cases, the instruction selector 70 // will pick deprecated instructions. 71 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">; 72 73 //===----------------------------------------------------------------------===// 74 // Instruction Pattern Stuff 75 //===----------------------------------------------------------------------===// 76 77 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 78 79 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 80 81 def LO10 : SDNodeXForm<imm, [{ 82 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N), 83 MVT::i32); 84 }]>; 85 86 def HI22 : SDNodeXForm<imm, [{ 87 // Transformation function: shift the immediate value down into the low bits. 88 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N), 89 MVT::i32); 90 }]>; 91 92 def SETHIimm : PatLeaf<(imm), [{ 93 return isShiftedUInt<22, 10>(N->getZExtValue()); 94 }], HI22>; 95 96 // Addressing modes. 97 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 98 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 99 100 // Address operands 101 def SparcMEMrrAsmOperand : AsmOperandClass { 102 let Name = "MEMrr"; 103 let ParserMethod = "parseMEMOperand"; 104 } 105 106 def SparcMEMriAsmOperand : AsmOperandClass { 107 let Name = "MEMri"; 108 let ParserMethod = "parseMEMOperand"; 109 } 110 111 def MEMrr : Operand<iPTR> { 112 let PrintMethod = "printMemOperand"; 113 let MIOperandInfo = (ops ptr_rc, ptr_rc); 114 let ParserMatchClass = SparcMEMrrAsmOperand; 115 } 116 def MEMri : Operand<iPTR> { 117 let PrintMethod = "printMemOperand"; 118 let MIOperandInfo = (ops ptr_rc, i32imm); 119 let ParserMatchClass = SparcMEMriAsmOperand; 120 } 121 122 def TLSSym : Operand<iPTR>; 123 124 // Branch targets have OtherVT type. 125 def brtarget : Operand<OtherVT> { 126 let EncoderMethod = "getBranchTargetOpValue"; 127 } 128 129 def bprtarget : Operand<OtherVT> { 130 let EncoderMethod = "getBranchPredTargetOpValue"; 131 } 132 133 def bprtarget16 : Operand<OtherVT> { 134 let EncoderMethod = "getBranchOnRegTargetOpValue"; 135 } 136 137 def calltarget : Operand<i32> { 138 let EncoderMethod = "getCallTargetOpValue"; 139 let DecoderMethod = "DecodeCall"; 140 } 141 142 def simm13Op : Operand<i32> { 143 let DecoderMethod = "DecodeSIMM13"; 144 } 145 146 // Operand for printing out a condition code. 147 let PrintMethod = "printCCOperand" in 148 def CCOp : Operand<i32>; 149 150 def SDTSPcmpicc : 151 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 152 def SDTSPcmpfcc : 153 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 154 def SDTSPbrcc : 155 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 156 def SDTSPselectcc : 157 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 158 def SDTSPFTOI : 159 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 160 def SDTSPITOF : 161 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 162 def SDTSPFTOX : 163 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>; 164 def SDTSPXTOF : 165 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>; 166 167 def SDTSPtlsadd : 168 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 169 def SDTSPtlsld : 170 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 171 172 def SDTSPeh_sjlj_setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 173 def SDTSPeh_sjlj_longjmp: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 174 175 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; 176 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 177 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 178 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 179 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 180 181 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 182 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 183 184 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 185 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 186 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>; 187 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>; 188 189 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 190 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 191 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 192 193 def SPsjlj_setjmp: SDNode<"SPISD::EH_SJLJ_SETJMP", 194 SDTSPeh_sjlj_setjmp, 195 [SDNPHasChain, SDNPSideEffect]>; 196 def SPsjlj_longjmp: SDNode<"SPISD::EH_SJLJ_LONGJMP", 197 SDTSPeh_sjlj_longjmp, 198 [SDNPHasChain, SDNPSideEffect]>; 199 200 // These are target-independent nodes, but have target-specific formats. 201 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 202 SDTCisVT<1, i32> ]>; 203 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 204 SDTCisVT<1, i32> ]>; 205 206 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 207 [SDNPHasChain, SDNPOutGlue]>; 208 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 209 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 210 211 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 212 def call : SDNode<"SPISD::CALL", SDT_SPCall, 213 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 214 SDNPVariadic]>; 215 216 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 217 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 218 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 219 220 def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 221 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 222 223 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>; 224 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>; 225 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall, 226 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 227 SDNPVariadic]>; 228 229 def getPCX : Operand<iPTR> { 230 let PrintMethod = "printGetPCX"; 231 } 232 233 //===----------------------------------------------------------------------===// 234 // SPARC Flag Conditions 235 //===----------------------------------------------------------------------===// 236 237 // Note that these values must be kept in sync with the CCOp::CondCode enum 238 // values. 239 class ICC_VAL<int N> : PatLeaf<(i32 N)>; 240 def ICC_NE : ICC_VAL< 9>; // Not Equal 241 def ICC_E : ICC_VAL< 1>; // Equal 242 def ICC_G : ICC_VAL<10>; // Greater 243 def ICC_LE : ICC_VAL< 2>; // Less or Equal 244 def ICC_GE : ICC_VAL<11>; // Greater or Equal 245 def ICC_L : ICC_VAL< 3>; // Less 246 def ICC_GU : ICC_VAL<12>; // Greater Unsigned 247 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 248 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 249 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 250 def ICC_POS : ICC_VAL<14>; // Positive 251 def ICC_NEG : ICC_VAL< 6>; // Negative 252 def ICC_VC : ICC_VAL<15>; // Overflow Clear 253 def ICC_VS : ICC_VAL< 7>; // Overflow Set 254 255 class FCC_VAL<int N> : PatLeaf<(i32 N)>; 256 def FCC_U : FCC_VAL<23>; // Unordered 257 def FCC_G : FCC_VAL<22>; // Greater 258 def FCC_UG : FCC_VAL<21>; // Unordered or Greater 259 def FCC_L : FCC_VAL<20>; // Less 260 def FCC_UL : FCC_VAL<19>; // Unordered or Less 261 def FCC_LG : FCC_VAL<18>; // Less or Greater 262 def FCC_NE : FCC_VAL<17>; // Not Equal 263 def FCC_E : FCC_VAL<25>; // Equal 264 def FCC_UE : FCC_VAL<26>; // Unordered or Equal 265 def FCC_GE : FCC_VAL<27>; // Greater or Equal 266 def FCC_UGE : FCC_VAL<28>; // Unordered or Greater or Equal 267 def FCC_LE : FCC_VAL<29>; // Less or Equal 268 def FCC_ULE : FCC_VAL<30>; // Unordered or Less or Equal 269 def FCC_O : FCC_VAL<31>; // Ordered 270 271 class CPCC_VAL<int N> : PatLeaf<(i32 N)>; 272 def CPCC_3 : CPCC_VAL<39>; // 3 273 def CPCC_2 : CPCC_VAL<38>; // 2 274 def CPCC_23 : CPCC_VAL<37>; // 2 or 3 275 def CPCC_1 : CPCC_VAL<36>; // 1 276 def CPCC_13 : CPCC_VAL<35>; // 1 or 3 277 def CPCC_12 : CPCC_VAL<34>; // 1 or 2 278 def CPCC_123 : CPCC_VAL<33>; // 1 or 2 or 3 279 def CPCC_0 : CPCC_VAL<41>; // 0 280 def CPCC_03 : CPCC_VAL<42>; // 0 or 3 281 def CPCC_02 : CPCC_VAL<43>; // 0 or 2 282 def CPCC_023 : CPCC_VAL<44>; // 0 or 2 or 3 283 def CPCC_01 : CPCC_VAL<45>; // 0 or 1 284 def CPCC_013 : CPCC_VAL<46>; // 0 or 1 or 3 285 def CPCC_012 : CPCC_VAL<47>; // 0 or 1 or 2 286 287 //===----------------------------------------------------------------------===// 288 // Instruction Class Templates 289 //===----------------------------------------------------------------------===// 290 291 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 292 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode, 293 RegisterClass RC, ValueType Ty, Operand immOp, 294 InstrItinClass itin = IIC_iu_instr> { 295 def rr : F3_1<2, Op3Val, 296 (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 297 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 298 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))], 299 itin>; 300 def ri : F3_2<2, Op3Val, 301 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13), 302 !strconcat(OpcStr, " $rs1, $simm13, $rd"), 303 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))], 304 itin>; 305 } 306 307 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 308 /// pattern. 309 multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> { 310 def rr : F3_1<2, Op3Val, 311 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 312 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [], 313 itin>; 314 def ri : F3_2<2, Op3Val, 315 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 316 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [], 317 itin>; 318 } 319 320 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. 321 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 322 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> { 323 def rr : F3_1<3, Op3Val, 324 (outs RC:$dst), (ins MEMrr:$addr), 325 !strconcat(OpcStr, " [$addr], $dst"), 326 [(set Ty:$dst, (OpNode ADDRrr:$addr))], 327 itin>; 328 def ri : F3_2<3, Op3Val, 329 (outs RC:$dst), (ins MEMri:$addr), 330 !strconcat(OpcStr, " [$addr], $dst"), 331 [(set Ty:$dst, (OpNode ADDRri:$addr))], 332 itin>; 333 } 334 335 // TODO: Instructions of the LoadASI class are currently asm only; hooking up 336 // CodeGen's address spaces to use these is a future task. 337 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 338 RegisterClass RC, ValueType Ty, InstrItinClass itin = NoItinerary> : 339 F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi), 340 !strconcat(OpcStr, "a [$addr] $asi, $dst"), 341 []>; 342 343 // LoadA multiclass - As above, but also define alternate address space variant 344 multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val, 345 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, 346 InstrItinClass itin = NoItinerary> : 347 Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> { 348 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>; 349 } 350 351 // The LDSTUB instruction is supported for asm only. 352 // It is unlikely that general-purpose code could make use of it. 353 // CAS is preferred for sparc v9. 354 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr), 355 "ldstub [$addr], $dst", []>; 356 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr), 357 "ldstub [$addr], $dst", []>; 358 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst), 359 (ins MEMrr:$addr, i8imm:$asi), 360 "ldstuba [$addr] $asi, $dst", []>; 361 362 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. 363 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 364 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> { 365 def rr : F3_1<3, Op3Val, 366 (outs), (ins MEMrr:$addr, RC:$rd), 367 !strconcat(OpcStr, " $rd, [$addr]"), 368 [(OpNode Ty:$rd, ADDRrr:$addr)], 369 itin>; 370 def ri : F3_2<3, Op3Val, 371 (outs), (ins MEMri:$addr, RC:$rd), 372 !strconcat(OpcStr, " $rd, [$addr]"), 373 [(OpNode Ty:$rd, ADDRri:$addr)], 374 itin>; 375 } 376 377 // TODO: Instructions of the StoreASI class are currently asm only; hooking up 378 // CodeGen's address spaces to use these is a future task. 379 class StoreASI<string OpcStr, bits<6> Op3Val, 380 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, 381 InstrItinClass itin = IIC_st> : 382 F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi), 383 !strconcat(OpcStr, "a $rd, [$addr] $asi"), 384 [], 385 itin>; 386 387 multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val, 388 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, 389 InstrItinClass itin = IIC_st> : 390 Store<OpcStr, Op3Val, OpNode, RC, Ty> { 391 def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty, itin>; 392 } 393 394 //===----------------------------------------------------------------------===// 395 // Instructions 396 //===----------------------------------------------------------------------===// 397 398 // Pseudo instructions. 399 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 400 : InstSP<outs, ins, asmstr, pattern> { 401 let isCodeGenOnly = 1; 402 let isPseudo = 1; 403 } 404 405 // GETPCX for PIC 406 let Defs = [O7] in { 407 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 408 } 409 410 let Defs = [O6], Uses = [O6] in { 411 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 412 "!ADJCALLSTACKDOWN $amt1, $amt2", 413 [(callseq_start timm:$amt1, timm:$amt2)]>; 414 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 415 "!ADJCALLSTACKUP $amt1", 416 [(callseq_end timm:$amt1, timm:$amt2)]>; 417 } 418 419 let hasSideEffects = 1, mayStore = 1 in { 420 let rd = 0, rs1 = 0, rs2 = 0 in 421 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 422 "flushw", 423 [(flushw)]>, Requires<[HasV9]>; 424 let rd = 8, rs1 = 0, simm13 = 3 in 425 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 426 "ta 3", 427 [(flushw)]>; 428 } 429 430 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 431 // instruction selection into a branch sequence. This has to handle all 432 // permutations of selection between i32/f32/f64 on ICC and FCC. 433 // Expanded after instruction selection. 434 let Uses = [ICC], usesCustomInserter = 1 in { 435 def SELECT_CC_Int_ICC 436 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 437 "; SELECT_CC_Int_ICC PSEUDO!", 438 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 439 def SELECT_CC_FP_ICC 440 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 441 "; SELECT_CC_FP_ICC PSEUDO!", 442 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 443 444 def SELECT_CC_DFP_ICC 445 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 446 "; SELECT_CC_DFP_ICC PSEUDO!", 447 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 448 449 def SELECT_CC_QFP_ICC 450 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 451 "; SELECT_CC_QFP_ICC PSEUDO!", 452 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>; 453 } 454 455 let usesCustomInserter = 1, Uses = [FCC0] in { 456 457 def SELECT_CC_Int_FCC 458 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 459 "; SELECT_CC_Int_FCC PSEUDO!", 460 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 461 462 def SELECT_CC_FP_FCC 463 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 464 "; SELECT_CC_FP_FCC PSEUDO!", 465 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 466 def SELECT_CC_DFP_FCC 467 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 468 "; SELECT_CC_DFP_FCC PSEUDO!", 469 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 470 def SELECT_CC_QFP_FCC 471 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 472 "; SELECT_CC_QFP_FCC PSEUDO!", 473 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>; 474 } 475 476 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 477 let Defs = [WIM] in 478 def EH_SJLJ_SETJMP32ri : Pseudo<(outs IntRegs:$dst), (ins MEMri:$buf), 479 "#EH_SJLJ_SETJMP32", 480 [(set i32:$dst, (SPsjlj_setjmp ADDRri:$buf))]>, 481 Requires<[Is32Bit]>; 482 def EH_SJLJ_SETJMP32rr : Pseudo<(outs IntRegs:$dst), (ins MEMrr:$buf), 483 "#EH_SJLJ_SETJMP32", 484 [(set i32:$dst, (SPsjlj_setjmp ADDRrr:$buf))]>, 485 Requires<[Is32Bit]>; 486 let isTerminator = 1 in 487 def EH_SJLJ_LONGJMP32ri : Pseudo<(outs), (ins MEMri:$buf), 488 "#EH_SJLJ_LONGJMP32", 489 [(SPsjlj_longjmp ADDRri:$buf)]>, 490 Requires<[Is32Bit]>; 491 def EH_SJLJ_LONGJMP32rr : Pseudo<(outs), (ins MEMrr:$buf), 492 "#EH_SJLJ_LONGJMP32", 493 [(SPsjlj_longjmp ADDRrr:$buf)]>, 494 Requires<[Is32Bit]>; 495 } 496 497 // Section B.1 - Load Integer Instructions, p. 90 498 let DecoderMethod = "DecodeLoadInt" in { 499 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>; 500 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>; 501 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>; 502 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>; 503 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>; 504 } 505 506 let DecoderMethod = "DecodeLoadIntPair" in 507 defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>; 508 509 // Section B.2 - Load Floating-point Instructions, p. 92 510 let DecoderMethod = "DecodeLoadFP" in { 511 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>; 512 def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32, IIC_iu_or_fpu_instr>, 513 Requires<[HasV9]>; 514 } 515 let DecoderMethod = "DecodeLoadDFP" in { 516 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64, IIC_ldd>; 517 def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>, 518 Requires<[HasV9]>; 519 } 520 let DecoderMethod = "DecodeLoadQFP" in 521 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>, 522 Requires<[HasV9, HasHardQuad]>; 523 524 let DecoderMethod = "DecodeLoadCP" in 525 defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>; 526 let DecoderMethod = "DecodeLoadCPPair" in 527 defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>; 528 529 let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in { 530 let rd = 0 in { 531 def LDCSRrr : F3_1<3, 0b110001, (outs), (ins MEMrr:$addr), 532 "ld [$addr], %csr", []>; 533 def LDCSRri : F3_2<3, 0b110001, (outs), (ins MEMri:$addr), 534 "ld [$addr], %csr", []>; 535 } 536 } 537 538 let DecoderMethod = "DecodeLoadFP" in 539 let Defs = [FSR] in { 540 let rd = 0 in { 541 def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), 542 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>; 543 def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr), 544 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>; 545 } 546 let rd = 1 in { 547 def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), 548 "ldx [$addr], %fsr", []>, Requires<[HasV9]>; 549 def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr), 550 "ldx [$addr], %fsr", []>, Requires<[HasV9]>; 551 } 552 } 553 554 // Section B.4 - Store Integer Instructions, p. 95 555 let DecoderMethod = "DecodeStoreInt" in { 556 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>; 557 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>; 558 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>; 559 } 560 561 let DecoderMethod = "DecodeStoreIntPair" in 562 defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>; 563 564 // Section B.5 - Store Floating-point Instructions, p. 97 565 let DecoderMethod = "DecodeStoreFP" in { 566 defm STF : Store<"st", 0b100100, store, FPRegs, f32>; 567 def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>, 568 Requires<[HasV9]>; 569 } 570 let DecoderMethod = "DecodeStoreDFP" in { 571 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64, IIC_std>; 572 def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>, 573 Requires<[HasV9]>; 574 } 575 let DecoderMethod = "DecodeStoreQFP" in 576 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>, 577 Requires<[HasV9, HasHardQuad]>; 578 579 let DecoderMethod = "DecodeStoreCP" in 580 defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>; 581 582 let DecoderMethod = "DecodeStoreCPPair" in 583 defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>; 584 585 let DecoderMethod = "DecodeStoreCP", rd = 0 in { 586 let Defs = [CPSR] in { 587 def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins), 588 "st %csr, [$addr]", [], IIC_st>; 589 def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins), 590 "st %csr, [$addr]", [], IIC_st>; 591 } 592 let Defs = [CPQ] in { 593 def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins), 594 "std %cq, [$addr]", [], IIC_std>; 595 def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins), 596 "std %cq, [$addr]", [], IIC_std>; 597 } 598 } 599 600 let DecoderMethod = "DecodeStoreFP" in { 601 let rd = 0 in { 602 let Defs = [FSR] in { 603 def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins), 604 "st %fsr, [$addr]", [], IIC_st>; 605 def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins), 606 "st %fsr, [$addr]", [], IIC_st>; 607 } 608 let Defs = [FQ] in { 609 def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins), 610 "std %fq, [$addr]", [], IIC_std>; 611 def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins), 612 "std %fq, [$addr]", [], IIC_std>; 613 } 614 } 615 let rd = 1, Defs = [FSR] in { 616 def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins), 617 "stx %fsr, [$addr]", []>, Requires<[HasV9]>; 618 def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins), 619 "stx %fsr, [$addr]", []>, Requires<[HasV9]>; 620 } 621 } 622 623 // Section B.8 - SWAP Register with Memory Instruction 624 // (Atomic swap) 625 let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in { 626 def SWAPrr : F3_1<3, 0b001111, 627 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val), 628 "swap [$addr], $dst", 629 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>; 630 def SWAPri : F3_2<3, 0b001111, 631 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val), 632 "swap [$addr], $dst", 633 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>; 634 def SWAPArr : F3_1_asi<3, 0b011111, 635 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val), 636 "swapa [$addr] $asi, $dst", 637 [/*FIXME: pattern?*/]>; 638 } 639 640 641 // Section B.9 - SETHI Instruction, p. 104 642 def SETHIi: F2_1<0b100, 643 (outs IntRegs:$rd), (ins i32imm:$imm22), 644 "sethi $imm22, $rd", 645 [(set i32:$rd, SETHIimm:$imm22)], 646 IIC_iu_instr>; 647 648 // Section B.10 - NOP Instruction, p. 105 649 // (It's a special case of SETHI) 650 let rd = 0, imm22 = 0 in 651 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 652 653 // Section B.11 - Logical Instructions, p. 106 654 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>; 655 656 def ANDNrr : F3_1<2, 0b000101, 657 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 658 "andn $rs1, $rs2, $rd", 659 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>; 660 def ANDNri : F3_2<2, 0b000101, 661 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 662 "andn $rs1, $simm13, $rd", []>; 663 664 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>; 665 666 def ORNrr : F3_1<2, 0b000110, 667 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 668 "orn $rs1, $rs2, $rd", 669 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>; 670 def ORNri : F3_2<2, 0b000110, 671 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 672 "orn $rs1, $simm13, $rd", []>; 673 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>; 674 675 def XNORrr : F3_1<2, 0b000111, 676 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 677 "xnor $rs1, $rs2, $rd", 678 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>; 679 def XNORri : F3_2<2, 0b000111, 680 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 681 "xnor $rs1, $simm13, $rd", []>; 682 683 let Defs = [ICC] in { 684 defm ANDCC : F3_12np<"andcc", 0b010001>; 685 defm ANDNCC : F3_12np<"andncc", 0b010101>; 686 defm ORCC : F3_12np<"orcc", 0b010010>; 687 defm ORNCC : F3_12np<"orncc", 0b010110>; 688 defm XORCC : F3_12np<"xorcc", 0b010011>; 689 defm XNORCC : F3_12np<"xnorcc", 0b010111>; 690 } 691 692 // Section B.12 - Shift Instructions, p. 107 693 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>; 694 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>; 695 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>; 696 697 // Section B.13 - Add Instructions, p. 108 698 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>; 699 700 // "LEA" forms of add (patterns to make tblgen happy) 701 let Predicates = [Is32Bit], isCodeGenOnly = 1 in 702 def LEA_ADDri : F3_2<2, 0b000000, 703 (outs IntRegs:$dst), (ins MEMri:$addr), 704 "add ${addr:arith}, $dst", 705 [(set iPTR:$dst, ADDRri:$addr)]>; 706 707 let Defs = [ICC] in 708 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>; 709 710 let Uses = [ICC] in 711 defm ADDC : F3_12np<"addx", 0b001000>; 712 713 let Uses = [ICC], Defs = [ICC] in 714 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>; 715 716 // Section B.15 - Subtract Instructions, p. 110 717 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>; 718 let Uses = [ICC], Defs = [ICC] in 719 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>; 720 721 let Defs = [ICC] in 722 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>; 723 724 let Uses = [ICC] in 725 defm SUBC : F3_12np <"subx", 0b001100>; 726 727 // cmp (from Section A.3) is a specialized alias for subcc 728 let Defs = [ICC], rd = 0 in { 729 def CMPrr : F3_1<2, 0b010100, 730 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 731 "cmp $rs1, $rs2", 732 [(SPcmpicc i32:$rs1, i32:$rs2)]>; 733 def CMPri : F3_2<2, 0b010100, 734 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 735 "cmp $rs1, $simm13", 736 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>; 737 } 738 739 // Section B.18 - Multiply Instructions, p. 113 740 let Defs = [Y] in { 741 defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>; 742 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>; 743 } 744 745 let Defs = [Y, ICC] in { 746 defm UMULCC : F3_12np<"umulcc", 0b011010, IIC_iu_umul>; 747 defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>; 748 } 749 750 let Defs = [Y, ICC], Uses = [Y, ICC] in { 751 defm MULSCC : F3_12np<"mulscc", 0b100100>; 752 } 753 754 // Section B.19 - Divide Instructions, p. 115 755 let Uses = [Y], Defs = [Y] in { 756 defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>; 757 defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>; 758 } 759 760 let Uses = [Y], Defs = [Y, ICC] in { 761 defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>; 762 defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>; 763 } 764 765 // Section B.20 - SAVE and RESTORE, p. 117 766 defm SAVE : F3_12np<"save" , 0b111100>; 767 defm RESTORE : F3_12np<"restore", 0b111101>; 768 769 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 770 771 // unconditional branch class. 772 class BranchAlways<dag ins, string asmstr, list<dag> pattern> 773 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> { 774 let isBranch = 1; 775 let isTerminator = 1; 776 let hasDelaySlot = 1; 777 let isBarrier = 1; 778 } 779 780 let cond = 8 in 781 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>; 782 783 784 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in { 785 786 // conditional branch class: 787 class BranchSP<dag ins, string asmstr, list<dag> pattern> 788 : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>; 789 790 // conditional branch with annul class: 791 class BranchSPA<dag ins, string asmstr, list<dag> pattern> 792 : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>; 793 794 // Conditional branch class on %icc|%xcc with predication: 795 multiclass IPredBranch<string regstr, list<dag> CCPattern> { 796 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond), 797 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")), 798 CCPattern, 799 IIC_iu_instr>; 800 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond), 801 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")), 802 [], 803 IIC_iu_instr>; 804 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond), 805 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")), 806 [], 807 IIC_iu_instr>; 808 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond), 809 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")), 810 [], 811 IIC_iu_instr>; 812 } 813 814 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 815 816 817 // Indirect branch instructions. 818 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1, 819 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in { 820 def BINDrr : F3_1<2, 0b111000, 821 (outs), (ins MEMrr:$ptr), 822 "jmp $ptr", 823 [(brind ADDRrr:$ptr)]>; 824 def BINDri : F3_2<2, 0b111000, 825 (outs), (ins MEMri:$ptr), 826 "jmp $ptr", 827 [(brind ADDRri:$ptr)]>; 828 } 829 830 let Uses = [ICC] in { 831 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond), 832 "b$cond $imm22", 833 [(SPbricc bb:$imm22, imm:$cond)]>; 834 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond), 835 "b$cond,a $imm22", []>; 836 837 let Predicates = [HasV9], cc = 0b00 in 838 defm BPI : IPredBranch<"%icc", []>; 839 } 840 841 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 842 843 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in { 844 845 // floating-point conditional branch class: 846 class FPBranchSP<dag ins, string asmstr, list<dag> pattern> 847 : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>; 848 849 // floating-point conditional branch with annul class: 850 class FPBranchSPA<dag ins, string asmstr, list<dag> pattern> 851 : F2_2<0b110, 1, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>; 852 853 // Conditional branch class on %fcc0-%fcc3 with predication: 854 multiclass FPredBranch { 855 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond, 856 FCCRegs:$cc), 857 "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>; 858 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond, 859 FCCRegs:$cc), 860 "fb$cond,a $cc, $imm19", [], IIC_fpu_normal_instr>; 861 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond, 862 FCCRegs:$cc), 863 "fb$cond,pn $cc, $imm19", [], IIC_fpu_normal_instr>; 864 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond, 865 FCCRegs:$cc), 866 "fb$cond,a,pn $cc, $imm19", [], IIC_fpu_normal_instr>; 867 } 868 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 869 870 let Uses = [FCC0] in { 871 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond), 872 "fb$cond $imm22", 873 [(SPbrfcc bb:$imm22, imm:$cond)]>; 874 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond), 875 "fb$cond,a $imm22", []>; 876 } 877 878 let Predicates = [HasV9] in 879 defm BPF : FPredBranch; 880 881 // Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123 882 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in { 883 884 // co-processor conditional branch class: 885 class CPBranchSP<dag ins, string asmstr, list<dag> pattern> 886 : F2_2<0b111, 0, (outs), ins, asmstr, pattern>; 887 888 // co-processor conditional branch with annul class: 889 class CPBranchSPA<dag ins, string asmstr, list<dag> pattern> 890 : F2_2<0b111, 1, (outs), ins, asmstr, pattern>; 891 892 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 893 894 def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond), 895 "cb$cond $imm22", 896 [(SPbrfcc bb:$imm22, imm:$cond)]>; 897 def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond), 898 "cb$cond,a $imm22", []>; 899 900 // Section B.24 - Call and Link Instruction, p. 125 901 // This is the only Format 1 instruction 902 let Uses = [O6], 903 hasDelaySlot = 1, isCall = 1 in { 904 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops), 905 "call $disp", 906 [], 907 IIC_jmp_or_call> { 908 bits<30> disp; 909 let op = 1; 910 let Inst{29-0} = disp; 911 } 912 913 // indirect calls: special cases of JMPL. 914 let isCodeGenOnly = 1, rd = 15 in { 915 def CALLrr : F3_1<2, 0b111000, 916 (outs), (ins MEMrr:$ptr, variable_ops), 917 "call $ptr", 918 [(call ADDRrr:$ptr)], 919 IIC_jmp_or_call>; 920 def CALLri : F3_2<2, 0b111000, 921 (outs), (ins MEMri:$ptr, variable_ops), 922 "call $ptr", 923 [(call ADDRri:$ptr)], 924 IIC_jmp_or_call>; 925 } 926 } 927 928 // Section B.25 - Jump and Link Instruction 929 930 // JMPL Instruction. 931 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, 932 DecoderMethod = "DecodeJMPL" in { 933 def JMPLrr: F3_1<2, 0b111000, 934 (outs IntRegs:$dst), (ins MEMrr:$addr), 935 "jmpl $addr, $dst", 936 [], 937 IIC_jmp_or_call>; 938 def JMPLri: F3_2<2, 0b111000, 939 (outs IntRegs:$dst), (ins MEMri:$addr), 940 "jmpl $addr, $dst", 941 [], 942 IIC_jmp_or_call>; 943 } 944 945 // Section A.3 - Synthetic Instructions, p. 85 946 // special cases of JMPL: 947 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, 948 isCodeGenOnly = 1 in { 949 let rd = 0, rs1 = 15 in 950 def RETL: F3_2<2, 0b111000, 951 (outs), (ins i32imm:$val), 952 "jmp %o7+$val", 953 [(retflag simm13:$val)], 954 IIC_jmp_or_call>; 955 956 let rd = 0, rs1 = 31 in 957 def RET: F3_2<2, 0b111000, 958 (outs), (ins i32imm:$val), 959 "jmp %i7+$val", 960 [], 961 IIC_jmp_or_call>; 962 } 963 964 // Section B.26 - Return from Trap Instruction 965 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, 966 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in { 967 def RETTrr : F3_1<2, 0b111001, 968 (outs), (ins MEMrr:$addr), 969 "rett $addr", 970 [], 971 IIC_jmp_or_call>; 972 def RETTri : F3_2<2, 0b111001, 973 (outs), (ins MEMri:$addr), 974 "rett $addr", 975 [], 976 IIC_jmp_or_call>; 977 } 978 979 980 // Section B.27 - Trap on Integer Condition Codes Instruction 981 // conditional branch class: 982 let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in 983 { 984 def TRAPrr : TRAPSPrr<0b111010, 985 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond), 986 "t$cond $rs1 + $rs2", 987 []>; 988 def TRAPri : TRAPSPri<0b111010, 989 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond), 990 "t$cond $rs1 + $imm", 991 []>; 992 } 993 994 multiclass TRAP<string regStr> { 995 def rr : TRAPSPrr<0b111010, 996 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond), 997 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), 998 []>; 999 def ri : TRAPSPri<0b111010, 1000 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond), 1001 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), 1002 []>; 1003 } 1004 1005 let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in 1006 defm TICC : TRAP<"%icc">; 1007 1008 1009 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in 1010 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>; 1011 1012 let hasSideEffects = 1, rd = 0b01000, rs1 = 0, simm13 = 1 in 1013 def TA1 : F3_2<0b10, 0b111010, (outs), (ins), "ta 1", [(debugtrap)]>; 1014 1015 // Section B.28 - Read State Register Instructions 1016 let rs2 = 0 in 1017 def RDASR : F3_1<2, 0b101000, 1018 (outs IntRegs:$rd), (ins ASRRegs:$rs1), 1019 "rd $rs1, $rd", []>; 1020 1021 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8. 1022 let Predicates = [HasNoV9] in { 1023 let rs2 = 0, rs1 = 0, Uses=[PSR] in 1024 def RDPSR : F3_1<2, 0b101001, 1025 (outs IntRegs:$rd), (ins), 1026 "rd %psr, $rd", []>; 1027 1028 let rs2 = 0, rs1 = 0, Uses=[WIM] in 1029 def RDWIM : F3_1<2, 0b101010, 1030 (outs IntRegs:$rd), (ins), 1031 "rd %wim, $rd", []>; 1032 1033 let rs2 = 0, rs1 = 0, Uses=[TBR] in 1034 def RDTBR : F3_1<2, 0b101011, 1035 (outs IntRegs:$rd), (ins), 1036 "rd %tbr, $rd", []>; 1037 } 1038 1039 // Section B.29 - Write State Register Instructions 1040 def WRASRrr : F3_1<2, 0b110000, 1041 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 1042 "wr $rs1, $rs2, $rd", []>; 1043 def WRASRri : F3_2<2, 0b110000, 1044 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 1045 "wr $rs1, $simm13, $rd", []>; 1046 1047 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8. 1048 let Predicates = [HasNoV9] in { 1049 let Defs = [PSR], rd=0 in { 1050 def WRPSRrr : F3_1<2, 0b110001, 1051 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1052 "wr $rs1, $rs2, %psr", []>; 1053 def WRPSRri : F3_2<2, 0b110001, 1054 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1055 "wr $rs1, $simm13, %psr", []>; 1056 } 1057 1058 let Defs = [WIM], rd=0 in { 1059 def WRWIMrr : F3_1<2, 0b110010, 1060 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1061 "wr $rs1, $rs2, %wim", []>; 1062 def WRWIMri : F3_2<2, 0b110010, 1063 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1064 "wr $rs1, $simm13, %wim", []>; 1065 } 1066 1067 let Defs = [TBR], rd=0 in { 1068 def WRTBRrr : F3_1<2, 0b110011, 1069 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1070 "wr $rs1, $rs2, %tbr", []>; 1071 def WRTBRri : F3_2<2, 0b110011, 1072 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1073 "wr $rs1, $simm13, %tbr", []>; 1074 } 1075 } 1076 1077 // Section B.30 - STBAR Instruction 1078 let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in 1079 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>; 1080 1081 1082 // Section B.31 - Unimplmented Instruction 1083 let rd = 0 in 1084 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22), 1085 "unimp $imm22", []>; 1086 1087 // Section B.32 - Flush Instruction Memory 1088 let rd = 0 in { 1089 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr), 1090 "flush $addr", []>; 1091 def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr), 1092 "flush $addr", []>; 1093 1094 // The no-arg FLUSH is only here for the benefit of the InstAlias 1095 // "flush", which cannot seem to use FLUSHrr, due to the inability 1096 // to construct a MEMrr with fixed G0 registers. 1097 let rs1 = 0, rs2 = 0 in 1098 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>; 1099 } 1100 1101 // Section B.33 - Floating-point Operate (FPop) Instructions 1102 1103 // Convert Integer to Floating-point Instructions, p. 141 1104 def FITOS : F3_3u<2, 0b110100, 0b011000100, 1105 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1106 "fitos $rs2, $rd", 1107 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))], 1108 IIC_fpu_fast_instr>; 1109 def FITOD : F3_3u<2, 0b110100, 0b011001000, 1110 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 1111 "fitod $rs2, $rd", 1112 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))], 1113 IIC_fpu_fast_instr>; 1114 def FITOQ : F3_3u<2, 0b110100, 0b011001100, 1115 (outs QFPRegs:$rd), (ins FPRegs:$rs2), 1116 "fitoq $rs2, $rd", 1117 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>, 1118 Requires<[HasHardQuad]>; 1119 1120 // Convert Floating-point to Integer Instructions, p. 142 1121 def FSTOI : F3_3u<2, 0b110100, 0b011010001, 1122 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1123 "fstoi $rs2, $rd", 1124 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))], 1125 IIC_fpu_fast_instr>; 1126 def FDTOI : F3_3u<2, 0b110100, 0b011010010, 1127 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 1128 "fdtoi $rs2, $rd", 1129 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))], 1130 IIC_fpu_fast_instr>; 1131 def FQTOI : F3_3u<2, 0b110100, 0b011010011, 1132 (outs FPRegs:$rd), (ins QFPRegs:$rs2), 1133 "fqtoi $rs2, $rd", 1134 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>, 1135 Requires<[HasHardQuad]>; 1136 1137 // Convert between Floating-point Formats Instructions, p. 143 1138 def FSTOD : F3_3u<2, 0b110100, 0b011001001, 1139 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 1140 "fstod $rs2, $rd", 1141 [(set f64:$rd, (fpextend f32:$rs2))], 1142 IIC_fpu_stod>; 1143 def FSTOQ : F3_3u<2, 0b110100, 0b011001101, 1144 (outs QFPRegs:$rd), (ins FPRegs:$rs2), 1145 "fstoq $rs2, $rd", 1146 [(set f128:$rd, (fpextend f32:$rs2))]>, 1147 Requires<[HasHardQuad]>; 1148 def FDTOS : F3_3u<2, 0b110100, 0b011000110, 1149 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 1150 "fdtos $rs2, $rd", 1151 [(set f32:$rd, (fpround f64:$rs2))], 1152 IIC_fpu_fast_instr>; 1153 def FDTOQ : F3_3u<2, 0b110100, 0b011001110, 1154 (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 1155 "fdtoq $rs2, $rd", 1156 [(set f128:$rd, (fpextend f64:$rs2))]>, 1157 Requires<[HasHardQuad]>; 1158 def FQTOS : F3_3u<2, 0b110100, 0b011000111, 1159 (outs FPRegs:$rd), (ins QFPRegs:$rs2), 1160 "fqtos $rs2, $rd", 1161 [(set f32:$rd, (fpround f128:$rs2))]>, 1162 Requires<[HasHardQuad]>; 1163 def FQTOD : F3_3u<2, 0b110100, 0b011001011, 1164 (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 1165 "fqtod $rs2, $rd", 1166 [(set f64:$rd, (fpround f128:$rs2))]>, 1167 Requires<[HasHardQuad]>; 1168 1169 // Floating-point Move Instructions, p. 144 1170 def FMOVS : F3_3u<2, 0b110100, 0b000000001, 1171 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1172 "fmovs $rs2, $rd", []>; 1173 def FNEGS : F3_3u<2, 0b110100, 0b000000101, 1174 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1175 "fnegs $rs2, $rd", 1176 [(set f32:$rd, (fneg f32:$rs2))], 1177 IIC_fpu_negs>; 1178 def FABSS : F3_3u<2, 0b110100, 0b000001001, 1179 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1180 "fabss $rs2, $rd", 1181 [(set f32:$rd, (fabs f32:$rs2))], 1182 IIC_fpu_abs>; 1183 1184 1185 // Floating-point Square Root Instructions, p.145 1186 // FSQRTS generates an erratum on LEON processors, so by disabling this instruction 1187 // this will be promoted to use FSQRTD with doubles instead. 1188 let Predicates = [HasNoFdivSqrtFix] in 1189 def FSQRTS : F3_3u<2, 0b110100, 0b000101001, 1190 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1191 "fsqrts $rs2, $rd", 1192 [(set f32:$rd, (fsqrt f32:$rs2))], 1193 IIC_fpu_sqrts>; 1194 def FSQRTD : F3_3u<2, 0b110100, 0b000101010, 1195 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1196 "fsqrtd $rs2, $rd", 1197 [(set f64:$rd, (fsqrt f64:$rs2))], 1198 IIC_fpu_sqrtd>; 1199 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011, 1200 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1201 "fsqrtq $rs2, $rd", 1202 [(set f128:$rd, (fsqrt f128:$rs2))]>, 1203 Requires<[HasHardQuad]>; 1204 1205 1206 1207 // Floating-point Add and Subtract Instructions, p. 146 1208 def FADDS : F3_3<2, 0b110100, 0b001000001, 1209 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1210 "fadds $rs1, $rs2, $rd", 1211 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))], 1212 IIC_fpu_fast_instr>; 1213 def FADDD : F3_3<2, 0b110100, 0b001000010, 1214 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1215 "faddd $rs1, $rs2, $rd", 1216 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))], 1217 IIC_fpu_fast_instr>; 1218 def FADDQ : F3_3<2, 0b110100, 0b001000011, 1219 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1220 "faddq $rs1, $rs2, $rd", 1221 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>, 1222 Requires<[HasHardQuad]>; 1223 1224 def FSUBS : F3_3<2, 0b110100, 0b001000101, 1225 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1226 "fsubs $rs1, $rs2, $rd", 1227 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))], 1228 IIC_fpu_fast_instr>; 1229 def FSUBD : F3_3<2, 0b110100, 0b001000110, 1230 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1231 "fsubd $rs1, $rs2, $rd", 1232 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))], 1233 IIC_fpu_fast_instr>; 1234 def FSUBQ : F3_3<2, 0b110100, 0b001000111, 1235 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1236 "fsubq $rs1, $rs2, $rd", 1237 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>, 1238 Requires<[HasHardQuad]>; 1239 1240 1241 // Floating-point Multiply and Divide Instructions, p. 147 1242 def FMULS : F3_3<2, 0b110100, 0b001001001, 1243 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1244 "fmuls $rs1, $rs2, $rd", 1245 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))], 1246 IIC_fpu_muls>, 1247 Requires<[HasFMULS]>; 1248 def FMULD : F3_3<2, 0b110100, 0b001001010, 1249 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1250 "fmuld $rs1, $rs2, $rd", 1251 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))], 1252 IIC_fpu_muld>; 1253 def FMULQ : F3_3<2, 0b110100, 0b001001011, 1254 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1255 "fmulq $rs1, $rs2, $rd", 1256 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>, 1257 Requires<[HasHardQuad]>; 1258 1259 def FSMULD : F3_3<2, 0b110100, 0b001101001, 1260 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1261 "fsmuld $rs1, $rs2, $rd", 1262 [(set f64:$rd, (fmul (fpextend f32:$rs1), 1263 (fpextend f32:$rs2)))], 1264 IIC_fpu_muld>, 1265 Requires<[HasFSMULD]>; 1266 def FDMULQ : F3_3<2, 0b110100, 0b001101110, 1267 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1268 "fdmulq $rs1, $rs2, $rd", 1269 [(set f128:$rd, (fmul (fpextend f64:$rs1), 1270 (fpextend f64:$rs2)))]>, 1271 Requires<[HasHardQuad]>; 1272 1273 // FDIVS generates an erratum on LEON processors, so by disabling this instruction 1274 // this will be promoted to use FDIVD with doubles instead. 1275 def FDIVS : F3_3<2, 0b110100, 0b001001101, 1276 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1277 "fdivs $rs1, $rs2, $rd", 1278 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))], 1279 IIC_fpu_divs>; 1280 def FDIVD : F3_3<2, 0b110100, 0b001001110, 1281 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1282 "fdivd $rs1, $rs2, $rd", 1283 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))], 1284 IIC_fpu_divd>; 1285 def FDIVQ : F3_3<2, 0b110100, 0b001001111, 1286 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1287 "fdivq $rs1, $rs2, $rd", 1288 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>, 1289 Requires<[HasHardQuad]>; 1290 1291 // Floating-point Compare Instructions, p. 148 1292 // Note: the 2nd template arg is different for these guys. 1293 // Note 2: the result of a FCMP is not available until the 2nd cycle 1294 // after the instr is retired, but there is no interlock in Sparc V8. 1295 // This behavior is modeled with a forced noop after the instruction in 1296 // DelaySlotFiller. 1297 1298 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in { 1299 def FCMPS : F3_3c<2, 0b110101, 0b001010001, 1300 (outs), (ins FPRegs:$rs1, FPRegs:$rs2), 1301 "fcmps $rs1, $rs2", 1302 [(SPcmpfcc f32:$rs1, f32:$rs2)], 1303 IIC_fpu_fast_instr>; 1304 def FCMPD : F3_3c<2, 0b110101, 0b001010010, 1305 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1306 "fcmpd $rs1, $rs2", 1307 [(SPcmpfcc f64:$rs1, f64:$rs2)], 1308 IIC_fpu_fast_instr>; 1309 def FCMPQ : F3_3c<2, 0b110101, 0b001010011, 1310 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1311 "fcmpq $rs1, $rs2", 1312 [(SPcmpfcc f128:$rs1, f128:$rs2)]>, 1313 Requires<[HasHardQuad]>; 1314 } 1315 1316 //===----------------------------------------------------------------------===// 1317 // Instructions for Thread Local Storage(TLS). 1318 //===----------------------------------------------------------------------===// 1319 let isCodeGenOnly = 1, isAsmParserOnly = 1 in { 1320 def TLS_ADDrr : F3_1<2, 0b000000, 1321 (outs IntRegs:$rd), 1322 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym), 1323 "add $rs1, $rs2, $rd, $sym", 1324 [(set i32:$rd, 1325 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>; 1326 1327 let mayLoad = 1 in 1328 def TLS_LDrr : F3_1<3, 0b000000, 1329 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), 1330 "ld [$addr], $dst, $sym", 1331 [(set i32:$dst, 1332 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 1333 1334 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in 1335 def TLS_CALL : InstSP<(outs), 1336 (ins calltarget:$disp, TLSSym:$sym, variable_ops), 1337 "call $disp, $sym", 1338 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)], 1339 IIC_jmp_or_call> { 1340 bits<30> disp; 1341 let op = 1; 1342 let Inst{29-0} = disp; 1343 } 1344 } 1345 1346 //===----------------------------------------------------------------------===// 1347 // V9 Instructions 1348 //===----------------------------------------------------------------------===// 1349 1350 // V9 Conditional Moves. 1351 let Predicates = [HasV9], Constraints = "$f = $rd" in { 1352 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 1353 let Uses = [ICC], intcc = 1, cc = 0b00 in { 1354 def MOVICCrr 1355 : F4_1<0b101100, (outs IntRegs:$rd), 1356 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 1357 "mov$cond %icc, $rs2, $rd", 1358 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>; 1359 1360 def MOVICCri 1361 : F4_2<0b101100, (outs IntRegs:$rd), 1362 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 1363 "mov$cond %icc, $simm11, $rd", 1364 [(set i32:$rd, 1365 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>; 1366 } 1367 1368 let Uses = [FCC0], intcc = 0, cc = 0b00 in { 1369 def MOVFCCrr 1370 : F4_1<0b101100, (outs IntRegs:$rd), 1371 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 1372 "mov$cond %fcc0, $rs2, $rd", 1373 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>; 1374 def MOVFCCri 1375 : F4_2<0b101100, (outs IntRegs:$rd), 1376 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 1377 "mov$cond %fcc0, $simm11, $rd", 1378 [(set i32:$rd, 1379 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>; 1380 } 1381 1382 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in { 1383 def FMOVS_ICC 1384 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 1385 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 1386 "fmovs$cond %icc, $rs2, $rd", 1387 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>; 1388 def FMOVD_ICC 1389 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 1390 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 1391 "fmovd$cond %icc, $rs2, $rd", 1392 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>; 1393 def FMOVQ_ICC 1394 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 1395 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 1396 "fmovq$cond %icc, $rs2, $rd", 1397 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>, 1398 Requires<[HasHardQuad]>; 1399 } 1400 1401 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in { 1402 def FMOVS_FCC 1403 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 1404 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 1405 "fmovs$cond %fcc0, $rs2, $rd", 1406 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>; 1407 def FMOVD_FCC 1408 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 1409 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 1410 "fmovd$cond %fcc0, $rs2, $rd", 1411 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>; 1412 def FMOVQ_FCC 1413 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 1414 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 1415 "fmovq$cond %fcc0, $rs2, $rd", 1416 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>, 1417 Requires<[HasHardQuad]>; 1418 } 1419 1420 } 1421 1422 // Floating-Point Move Instructions, p. 164 of the V9 manual. 1423 let Predicates = [HasV9] in { 1424 def FMOVD : F3_3u<2, 0b110100, 0b000000010, 1425 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1426 "fmovd $rs2, $rd", []>; 1427 def FMOVQ : F3_3u<2, 0b110100, 0b000000011, 1428 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1429 "fmovq $rs2, $rd", []>, 1430 Requires<[HasHardQuad]>; 1431 def FNEGD : F3_3u<2, 0b110100, 0b000000110, 1432 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1433 "fnegd $rs2, $rd", 1434 [(set f64:$rd, (fneg f64:$rs2))]>; 1435 def FNEGQ : F3_3u<2, 0b110100, 0b000000111, 1436 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1437 "fnegq $rs2, $rd", 1438 [(set f128:$rd, (fneg f128:$rs2))]>, 1439 Requires<[HasHardQuad]>; 1440 def FABSD : F3_3u<2, 0b110100, 0b000001010, 1441 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1442 "fabsd $rs2, $rd", 1443 [(set f64:$rd, (fabs f64:$rs2))]>; 1444 def FABSQ : F3_3u<2, 0b110100, 0b000001011, 1445 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1446 "fabsq $rs2, $rd", 1447 [(set f128:$rd, (fabs f128:$rs2))]>, 1448 Requires<[HasHardQuad]>; 1449 } 1450 1451 // Floating-point compare instruction with %fcc0-%fcc3. 1452 def V9FCMPS : F3_3c<2, 0b110101, 0b001010001, 1453 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1454 "fcmps $rd, $rs1, $rs2", []>; 1455 def V9FCMPD : F3_3c<2, 0b110101, 0b001010010, 1456 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1457 "fcmpd $rd, $rs1, $rs2", []>; 1458 def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011, 1459 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1460 "fcmpq $rd, $rs1, $rs2", []>, 1461 Requires<[HasHardQuad]>; 1462 1463 let hasSideEffects = 1 in { 1464 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101, 1465 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1466 "fcmpes $rd, $rs1, $rs2", []>; 1467 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110, 1468 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1469 "fcmped $rd, $rs1, $rs2", []>; 1470 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111, 1471 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1472 "fcmpeq $rd, $rs1, $rs2", []>, 1473 Requires<[HasHardQuad]>; 1474 } 1475 1476 // Floating point conditional move instrucitons with %fcc0-%fcc3. 1477 let Predicates = [HasV9] in { 1478 let Constraints = "$f = $rd", intcc = 0 in { 1479 def V9MOVFCCrr 1480 : F4_1<0b101100, (outs IntRegs:$rd), 1481 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 1482 "mov$cond $cc, $rs2, $rd", []>; 1483 def V9MOVFCCri 1484 : F4_2<0b101100, (outs IntRegs:$rd), 1485 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond), 1486 "mov$cond $cc, $simm11, $rd", []>; 1487 def V9FMOVS_FCC 1488 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 1489 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 1490 "fmovs$cond $opf_cc, $rs2, $rd", []>; 1491 def V9FMOVD_FCC 1492 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 1493 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 1494 "fmovd$cond $opf_cc, $rs2, $rd", []>; 1495 def V9FMOVQ_FCC 1496 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 1497 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 1498 "fmovq$cond $opf_cc, $rs2, $rd", []>, 1499 Requires<[HasHardQuad]>; 1500 } // Constraints = "$f = $rd", ... 1501 } // let Predicates = [hasV9] 1502 1503 1504 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 1505 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0. 1506 let rs1 = 0 in 1507 def POPCrr : F3_1<2, 0b101110, 1508 (outs IntRegs:$rd), (ins IntRegs:$rs2), 1509 "popc $rs2, $rd", []>, Requires<[HasV9]>; 1510 def : Pat<(ctpop i32:$src), 1511 (POPCrr (SRLri $src, 0))>; 1512 1513 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in 1514 def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13), 1515 "membar $simm13", []>; 1516 1517 // The CAS instruction, unlike other instructions, only comes in a 1518 // form which requires an ASI be provided. The ASI value hardcoded 1519 // here is ASI_PRIMARY, the default unprivileged ASI for SparcV9. 1520 let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in 1521 def CASrr: F3_1_asi<3, 0b111100, 1522 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 1523 IntRegs:$swap), 1524 "cas [$rs1], $rs2, $rd", 1525 [(set i32:$rd, 1526 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>; 1527 1528 1529 // CASA is supported as an instruction on some LEON3 and all LEON4 processors. 1530 // This version can be automatically lowered from C code, selecting ASI 10 1531 let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in 1532 def CASAasi10: F3_1_asi<3, 0b111100, 1533 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 1534 IntRegs:$swap), 1535 "casa [$rs1] 10, $rs2, $rd", 1536 [(set i32:$rd, 1537 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>; 1538 1539 // CASA supported on some LEON3 and all LEON4 processors. Same pattern as 1540 // CASrr, above, but with a different ASI. This version is supported for 1541 // inline assembly lowering only. 1542 let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in 1543 def CASArr: F3_1_asi<3, 0b111100, 1544 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 1545 IntRegs:$swap, i8imm:$asi), 1546 "casa [$rs1] $asi, $rs2, $rd", []>; 1547 1548 // TODO: Add DAG sequence to lower these instructions. Currently, only provided 1549 // as inline assembler-supported instructions. 1550 let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in { 1551 def SMACrr : F3_1<2, 0b111111, 1552 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), 1553 "smac $rs1, $rs2, $rd", 1554 [], IIC_smac_umac>; 1555 1556 def SMACri : F3_2<2, 0b111111, 1557 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), 1558 "smac $rs1, $simm13, $rd", 1559 [], IIC_smac_umac>; 1560 1561 def UMACrr : F3_1<2, 0b111110, 1562 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), 1563 "umac $rs1, $rs2, $rd", 1564 [], IIC_smac_umac>; 1565 1566 def UMACri : F3_2<2, 0b111110, 1567 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), 1568 "umac $rs1, $simm13, $rd", 1569 [], IIC_smac_umac>; 1570 } 1571 1572 let Defs = [ICC] in { 1573 defm TADDCC : F3_12np<"taddcc", 0b100000>; 1574 defm TSUBCC : F3_12np<"tsubcc", 0b100001>; 1575 1576 let hasSideEffects = 1 in { 1577 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>; 1578 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>; 1579 } 1580 } 1581 1582 1583 // Section A.43 - Read Privileged Register Instructions 1584 let Predicates = [HasV9] in { 1585 let rs2 = 0 in 1586 def RDPR : F3_1<2, 0b101010, 1587 (outs IntRegs:$rd), (ins PRRegs:$rs1), 1588 "rdpr $rs1, $rd", []>; 1589 } 1590 1591 // Section A.62 - Write Privileged Register Instructions 1592 let Predicates = [HasV9] in { 1593 def WRPRrr : F3_1<2, 0b110010, 1594 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 1595 "wrpr $rs1, $rs2, $rd", []>; 1596 def WRPRri : F3_2<2, 0b110010, 1597 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 1598 "wrpr $rs1, $simm13, $rd", []>; 1599 } 1600 1601 //===----------------------------------------------------------------------===// 1602 // Non-Instruction Patterns 1603 //===----------------------------------------------------------------------===// 1604 1605 // Zero immediate. 1606 def : Pat<(i32 0), 1607 (ORrr (i32 G0), (i32 G0))>; 1608 // Small immediates. 1609 def : Pat<(i32 simm13:$val), 1610 (ORri (i32 G0), imm:$val)>; 1611 // Arbitrary immediates. 1612 def : Pat<(i32 imm:$val), 1613 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 1614 1615 1616 // Global addresses, constant pool entries 1617 let Predicates = [Is32Bit] in { 1618 1619 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 1620 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 1621 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 1622 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 1623 1624 // GlobalTLS addresses 1625 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 1626 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>; 1627 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 1628 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 1629 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 1630 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 1631 1632 // Blockaddress 1633 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 1634 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 1635 1636 // Add reg, lo. This is used when taking the addr of a global/constpool entry. 1637 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 1638 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 1639 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 1640 (ADDri $r, tblockaddress:$in)>; 1641 } 1642 1643 // Calls: 1644 def : Pat<(call tglobaladdr:$dst), 1645 (CALL tglobaladdr:$dst)>; 1646 def : Pat<(call texternalsym:$dst), 1647 (CALL texternalsym:$dst)>; 1648 1649 // Map integer extload's to zextloads. 1650 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1651 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1652 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1653 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1654 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 1655 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 1656 1657 // zextload bool -> zextload byte 1658 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1659 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1660 1661 // store 0, addr -> store %g0, addr 1662 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 1663 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 1664 1665 // store bar for all atomic_fence in V8. 1666 let Predicates = [HasNoV9] in 1667 def : Pat<(atomic_fence imm, imm), (STBAR)>; 1668 1669 // atomic_load addr -> load addr 1670 def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1671 def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1672 def : Pat<(i32 (atomic_load_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 1673 def : Pat<(i32 (atomic_load_16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 1674 def : Pat<(i32 (atomic_load_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>; 1675 def : Pat<(i32 (atomic_load_32 ADDRri:$src)), (LDri ADDRri:$src)>; 1676 1677 // atomic_store val, addr -> store val, addr 1678 def : Pat<(atomic_store_8 ADDRrr:$dst, i32:$val), (STBrr ADDRrr:$dst, $val)>; 1679 def : Pat<(atomic_store_8 ADDRri:$dst, i32:$val), (STBri ADDRri:$dst, $val)>; 1680 def : Pat<(atomic_store_16 ADDRrr:$dst, i32:$val), (STHrr ADDRrr:$dst, $val)>; 1681 def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>; 1682 def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>; 1683 def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>; 1684 1685 // extract_vector 1686 def : Pat<(extractelt (v2i32 IntPair:$Rn), 0), 1687 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>; 1688 def : Pat<(extractelt (v2i32 IntPair:$Rn), 1), 1689 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>; 1690 1691 // build_vector 1692 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)), 1693 (INSERT_SUBREG 1694 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even), 1695 (i32 IntRegs:$a2), sub_odd)>; 1696 1697 1698 include "SparcInstr64Bit.td" 1699 include "SparcInstrVIS.td" 1700 include "SparcInstrAliases.td" 1701
