1 //==- SystemZInstrHFP.td - Floating-point SystemZ instructions -*- tblgen-*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // The instructions in this file implement SystemZ hexadecimal floating-point 11 // arithmetic. Since this format is not mapped to any source-language data 12 // type, these instructions are not used for code generation, but are provided 13 // for use with the assembler and disassembler only. 14 // 15 //===----------------------------------------------------------------------===// 16 17 //===----------------------------------------------------------------------===// 18 // Move instructions 19 //===----------------------------------------------------------------------===// 20 21 // Load and test. 22 let Defs = [CC] in { 23 def LTER : UnaryRR <"lter", 0x32, null_frag, FP32, FP32>; 24 def LTDR : UnaryRR <"ltdr", 0x22, null_frag, FP64, FP64>; 25 def LTXR : UnaryRRE<"ltxr", 0xB362, null_frag, FP128, FP128>; 26 } 27 28 //===----------------------------------------------------------------------===// 29 // Conversion instructions 30 //===----------------------------------------------------------------------===// 31 32 // Convert floating-point values to narrower representations. 33 def LEDR : UnaryRR <"ledr", 0x35, null_frag, FP32, FP64>; 34 def LEXR : UnaryRRE<"lexr", 0xB366, null_frag, FP32, FP128>; 35 def LDXR : UnaryRR <"ldxr", 0x25, null_frag, FP64, FP128>; 36 let isAsmParserOnly = 1 in { 37 def LRER : UnaryRR <"lrer", 0x35, null_frag, FP32, FP64>; 38 def LRDR : UnaryRR <"lrdr", 0x25, null_frag, FP64, FP128>; 39 } 40 41 // Extend floating-point values to wider representations. 42 def LDER : UnaryRRE<"lder", 0xB324, null_frag, FP64, FP32>; 43 def LXER : UnaryRRE<"lxer", 0xB326, null_frag, FP128, FP32>; 44 def LXDR : UnaryRRE<"lxdr", 0xB325, null_frag, FP128, FP64>; 45 46 def LDE : UnaryRXE<"lde", 0xED24, null_frag, FP64, 4>; 47 def LXE : UnaryRXE<"lxe", 0xED26, null_frag, FP128, 4>; 48 def LXD : UnaryRXE<"lxd", 0xED25, null_frag, FP128, 8>; 49 50 // Convert a signed integer register value to a floating-point one. 51 def CEFR : UnaryRRE<"cefr", 0xB3B4, null_frag, FP32, GR32>; 52 def CDFR : UnaryRRE<"cdfr", 0xB3B5, null_frag, FP64, GR32>; 53 def CXFR : UnaryRRE<"cxfr", 0xB3B6, null_frag, FP128, GR32>; 54 55 def CEGR : UnaryRRE<"cegr", 0xB3C4, null_frag, FP32, GR64>; 56 def CDGR : UnaryRRE<"cdgr", 0xB3C5, null_frag, FP64, GR64>; 57 def CXGR : UnaryRRE<"cxgr", 0xB3C6, null_frag, FP128, GR64>; 58 59 // Convert a floating-point register value to a signed integer value, 60 // with the second operand (modifier M3) specifying the rounding mode. 61 let Defs = [CC] in { 62 def CFER : BinaryRRFe<"cfer", 0xB3B8, GR32, FP32>; 63 def CFDR : BinaryRRFe<"cfdr", 0xB3B9, GR32, FP64>; 64 def CFXR : BinaryRRFe<"cfxr", 0xB3BA, GR32, FP128>; 65 66 def CGER : BinaryRRFe<"cger", 0xB3C8, GR64, FP32>; 67 def CGDR : BinaryRRFe<"cgdr", 0xB3C9, GR64, FP64>; 68 def CGXR : BinaryRRFe<"cgxr", 0xB3CA, GR64, FP128>; 69 } 70 71 // Convert BFP to HFP. 72 let Defs = [CC] in { 73 def THDER : UnaryRRE<"thder", 0xB358, null_frag, FP64, FP32>; 74 def THDR : UnaryRRE<"thdr", 0xB359, null_frag, FP64, FP64>; 75 } 76 77 // Convert HFP to BFP. 78 let Defs = [CC] in { 79 def TBEDR : BinaryRRFe<"tbedr", 0xB350, FP32, FP64>; 80 def TBDR : BinaryRRFe<"tbdr", 0xB351, FP64, FP64>; 81 } 82 83 84 //===----------------------------------------------------------------------===// 85 // Unary arithmetic 86 //===----------------------------------------------------------------------===// 87 88 // Negation (Load Complement). 89 let Defs = [CC] in { 90 def LCER : UnaryRR <"lcer", 0x33, null_frag, FP32, FP32>; 91 def LCDR : UnaryRR <"lcdr", 0x23, null_frag, FP64, FP64>; 92 def LCXR : UnaryRRE<"lcxr", 0xB363, null_frag, FP128, FP128>; 93 } 94 95 // Absolute value (Load Positive). 96 let Defs = [CC] in { 97 def LPER : UnaryRR <"lper", 0x30, null_frag, FP32, FP32>; 98 def LPDR : UnaryRR <"lpdr", 0x20, null_frag, FP64, FP64>; 99 def LPXR : UnaryRRE<"lpxr", 0xB360, null_frag, FP128, FP128>; 100 } 101 102 // Negative absolute value (Load Negative). 103 let Defs = [CC] in { 104 def LNER : UnaryRR <"lner", 0x31, null_frag, FP32, FP32>; 105 def LNDR : UnaryRR <"lndr", 0x21, null_frag, FP64, FP64>; 106 def LNXR : UnaryRRE<"lnxr", 0xB361, null_frag, FP128, FP128>; 107 } 108 109 // Halve. 110 def HER : UnaryRR <"her", 0x34, null_frag, FP32, FP32>; 111 def HDR : UnaryRR <"hdr", 0x24, null_frag, FP64, FP64>; 112 113 // Square root. 114 def SQER : UnaryRRE<"sqer", 0xB245, null_frag, FP32, FP32>; 115 def SQDR : UnaryRRE<"sqdr", 0xB244, null_frag, FP64, FP64>; 116 def SQXR : UnaryRRE<"sqxr", 0xB336, null_frag, FP128, FP128>; 117 118 def SQE : UnaryRXE<"sqe", 0xED34, null_frag, FP32, 4>; 119 def SQD : UnaryRXE<"sqd", 0xED35, null_frag, FP64, 8>; 120 121 // Round to an integer (rounding towards zero). 122 def FIER : UnaryRRE<"fier", 0xB377, null_frag, FP32, FP32>; 123 def FIDR : UnaryRRE<"fidr", 0xB37F, null_frag, FP64, FP64>; 124 def FIXR : UnaryRRE<"fixr", 0xB367, null_frag, FP128, FP128>; 125 126 127 //===----------------------------------------------------------------------===// 128 // Binary arithmetic 129 //===----------------------------------------------------------------------===// 130 131 // Addition. 132 let Defs = [CC] in { 133 let isCommutable = 1 in { 134 def AER : BinaryRR<"aer", 0x3A, null_frag, FP32, FP32>; 135 def ADR : BinaryRR<"adr", 0x2A, null_frag, FP64, FP64>; 136 def AXR : BinaryRR<"axr", 0x36, null_frag, FP128, FP128>; 137 } 138 def AE : BinaryRX<"ae", 0x7A, null_frag, FP32, load, 4>; 139 def AD : BinaryRX<"ad", 0x6A, null_frag, FP64, load, 8>; 140 } 141 142 // Addition (unnormalized). 143 let Defs = [CC] in { 144 let isCommutable = 1 in { 145 def AUR : BinaryRR<"aur", 0x3E, null_frag, FP32, FP32>; 146 def AWR : BinaryRR<"awr", 0x2E, null_frag, FP64, FP64>; 147 } 148 def AU : BinaryRX<"au", 0x7E, null_frag, FP32, load, 4>; 149 def AW : BinaryRX<"aw", 0x6E, null_frag, FP64, load, 8>; 150 } 151 152 // Subtraction. 153 let Defs = [CC] in { 154 def SER : BinaryRR<"ser", 0x3B, null_frag, FP32, FP32>; 155 def SDR : BinaryRR<"sdr", 0x2B, null_frag, FP64, FP64>; 156 def SXR : BinaryRR<"sxr", 0x37, null_frag, FP128, FP128>; 157 158 def SE : BinaryRX<"se", 0x7B, null_frag, FP32, load, 4>; 159 def SD : BinaryRX<"sd", 0x6B, null_frag, FP64, load, 8>; 160 } 161 162 // Subtraction (unnormalized). 163 let Defs = [CC] in { 164 def SUR : BinaryRR<"sur", 0x3F, null_frag, FP32, FP32>; 165 def SWR : BinaryRR<"swr", 0x2F, null_frag, FP64, FP64>; 166 167 def SU : BinaryRX<"su", 0x7F, null_frag, FP32, load, 4>; 168 def SW : BinaryRX<"sw", 0x6F, null_frag, FP64, load, 8>; 169 } 170 171 // Multiplication. 172 let isCommutable = 1 in { 173 def MEER : BinaryRRE<"meer", 0xB337, null_frag, FP32, FP32>; 174 def MDR : BinaryRR <"mdr", 0x2C, null_frag, FP64, FP64>; 175 def MXR : BinaryRR <"mxr", 0x26, null_frag, FP128, FP128>; 176 } 177 def MEE : BinaryRXE<"mee", 0xED37, null_frag, FP32, load, 4>; 178 def MD : BinaryRX <"md", 0x6C, null_frag, FP64, load, 8>; 179 180 // Extending multiplication (f32 x f32 -> f64). 181 def MDER : BinaryRR<"mder", 0x3C, null_frag, FP64, FP32>; 182 def MDE : BinaryRX<"mde", 0x7C, null_frag, FP64, load, 4>; 183 let isAsmParserOnly = 1 in { 184 def MER : BinaryRR<"mer", 0x3C, null_frag, FP64, FP32>; 185 def ME : BinaryRX<"me", 0x7C, null_frag, FP64, load, 4>; 186 } 187 188 // Extending multiplication (f64 x f64 -> f128). 189 def MXDR : BinaryRR<"mxdr", 0x27, null_frag, FP128, FP64>; 190 def MXD : BinaryRX<"mxd", 0x67, null_frag, FP128, load, 8>; 191 192 // Fused multiply-add. 193 def MAER : TernaryRRD<"maer", 0xB32E, null_frag, FP32, FP32>; 194 def MADR : TernaryRRD<"madr", 0xB33E, null_frag, FP64, FP64>; 195 def MAE : TernaryRXF<"mae", 0xED2E, null_frag, FP32, FP32, load, 4>; 196 def MAD : TernaryRXF<"mad", 0xED3E, null_frag, FP64, FP64, load, 8>; 197 198 // Fused multiply-subtract. 199 def MSER : TernaryRRD<"mser", 0xB32F, null_frag, FP32, FP32>; 200 def MSDR : TernaryRRD<"msdr", 0xB33F, null_frag, FP64, FP64>; 201 def MSE : TernaryRXF<"mse", 0xED2F, null_frag, FP32, FP32, load, 4>; 202 def MSD : TernaryRXF<"msd", 0xED3F, null_frag, FP64, FP64, load, 8>; 203 204 // Multiplication (unnormalized). 205 def MYR : BinaryRRD<"myr", 0xB33B, null_frag, FP128, FP64>; 206 def MYHR : BinaryRRD<"myhr", 0xB33D, null_frag, FP64, FP64>; 207 def MYLR : BinaryRRD<"mylr", 0xB339, null_frag, FP64, FP64>; 208 def MY : BinaryRXF<"my", 0xED3B, null_frag, FP128, FP64, load, 8>; 209 def MYH : BinaryRXF<"myh", 0xED3D, null_frag, FP64, FP64, load, 8>; 210 def MYL : BinaryRXF<"myl", 0xED39, null_frag, FP64, FP64, load, 8>; 211 212 // Fused multiply-add (unnormalized). 213 def MAYR : TernaryRRD<"mayr", 0xB33A, null_frag, FP128, FP64>; 214 def MAYHR : TernaryRRD<"mayhr", 0xB33C, null_frag, FP64, FP64>; 215 def MAYLR : TernaryRRD<"maylr", 0xB338, null_frag, FP64, FP64>; 216 def MAY : TernaryRXF<"may", 0xED3A, null_frag, FP128, FP64, load, 8>; 217 def MAYH : TernaryRXF<"mayh", 0xED3C, null_frag, FP64, FP64, load, 8>; 218 def MAYL : TernaryRXF<"mayl", 0xED38, null_frag, FP64, FP64, load, 8>; 219 220 // Division. 221 def DER : BinaryRR <"der", 0x3D, null_frag, FP32, FP32>; 222 def DDR : BinaryRR <"ddr", 0x2D, null_frag, FP64, FP64>; 223 def DXR : BinaryRRE<"dxr", 0xB22D, null_frag, FP128, FP128>; 224 def DE : BinaryRX <"de", 0x7D, null_frag, FP32, load, 4>; 225 def DD : BinaryRX <"dd", 0x6D, null_frag, FP64, load, 8>; 226 227 228 //===----------------------------------------------------------------------===// 229 // Comparisons 230 //===----------------------------------------------------------------------===// 231 232 let Defs = [CC] in { 233 def CER : CompareRR <"cer", 0x39, null_frag, FP32, FP32>; 234 def CDR : CompareRR <"cdr", 0x29, null_frag, FP64, FP64>; 235 def CXR : CompareRRE<"cxr", 0xB369, null_frag, FP128, FP128>; 236 237 def CE : CompareRX<"ce", 0x79, null_frag, FP32, load, 4>; 238 def CD : CompareRX<"cd", 0x69, null_frag, FP64, load, 8>; 239 } 240 241
