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      1 //=- SystemZScheduleZEC12.td - SystemZ Scheduling Definitions --*- tblgen -*-=//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the machine model for ZEC12 to support instruction
     11 // scheduling and other instruction cost heuristics.
     12 //
     13 // Pseudos expanded right after isel do not need to be modelled here.
     14 //
     15 //===----------------------------------------------------------------------===//
     16 
     17 def ZEC12Model : SchedMachineModel {
     18 
     19     let UnsupportedFeatures = Arch10UnsupportedFeatures.List;
     20     
     21     let IssueWidth = 3;
     22     let MicroOpBufferSize = 40;     // Issue queues
     23     let LoadLatency = 1;            // Optimistic load latency.
     24 
     25     let PostRAScheduler = 1;
     26 
     27     // Extra cycles for a mispredicted branch.
     28     let MispredictPenalty = 16;
     29 }
     30 
     31 let SchedModel = ZEC12Model in {
     32 // These definitions need the SchedModel value. They could be put in a
     33 // subtarget common include file, but it seems the include system in Tablegen
     34 // currently (2016) rejects multiple includes of same file.
     35 
     36 // Decoder grouping rules
     37 let NumMicroOps = 1 in {
     38   def : WriteRes<NormalGr, []>;
     39   def : WriteRes<BeginGroup, []> { let BeginGroup  = 1; }
     40   def : WriteRes<EndGroup, []>   { let EndGroup    = 1; }
     41 }
     42 def : WriteRes<Cracked, []> {
     43   let NumMicroOps = 2;
     44   let BeginGroup  = 1;
     45 }
     46 def : WriteRes<GroupAlone, []> {
     47   let NumMicroOps = 3;
     48   let BeginGroup  = 1;
     49   let EndGroup    = 1;
     50 }
     51 
     52 // Incoming latency removed from the register operand which is used together
     53 // with a memory operand by the instruction.
     54 def : ReadAdvance<RegReadAdv, 4>;
     55 
     56 // LoadLatency (above) is not used for instructions in this file. This is
     57 // instead the role of LSULatency, which is the latency value added to the
     58 // result of loads and instructions with folded memory operands.
     59 def : WriteRes<LSULatency, []> { let Latency = 4; let NumMicroOps = 0; }
     60 
     61 let NumMicroOps = 0 in {
     62   foreach L = 1-30 in {
     63     def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
     64   }
     65 }
     66 
     67 // Execution units.
     68 def ZEC12_FXUnit : ProcResource<2>;
     69 def ZEC12_LSUnit : ProcResource<2>;
     70 def ZEC12_FPUnit : ProcResource<1>;
     71 def ZEC12_DFUnit : ProcResource<1>;
     72 def ZEC12_VBUnit : ProcResource<1>;
     73 def ZEC12_MCD    : ProcResource<1>;
     74 
     75 // Subtarget specific definitions of scheduling resources.
     76 let NumMicroOps = 0 in {
     77   def : WriteRes<FXU, [ZEC12_FXUnit]>;
     78   def : WriteRes<LSU, [ZEC12_LSUnit]>;
     79   def : WriteRes<FPU, [ZEC12_FPUnit]>;
     80   def : WriteRes<DFU, [ZEC12_DFUnit]>;
     81   foreach Num = 2-6 in { let ResourceCycles = [Num] in {
     82     def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
     83     def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
     84     def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
     85     def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;
     86   }}
     87 
     88   def : WriteRes<VBU,  [ZEC12_VBUnit]>; // Virtual Branching Unit
     89 }
     90 
     91 def : WriteRes<MCD, [ZEC12_MCD]> { let NumMicroOps = 3;
     92                                    let BeginGroup  = 1;
     93                                    let EndGroup    = 1; }
     94 
     95 // -------------------------- INSTRUCTIONS ---------------------------------- //
     96 
     97 // InstRW constructs have been used in order to preserve the
     98 // readability of the InstrInfo files.
     99 
    100 // For each instruction, as matched by a regexp, provide a list of
    101 // resources that it needs. These will be combined into a SchedClass.
    102 
    103 //===----------------------------------------------------------------------===//
    104 // Stack allocation
    105 //===----------------------------------------------------------------------===//
    106 
    107 // Pseudo -> LA / LAY
    108 def : InstRW<[WLat1, FXU, NormalGr], (instregex "ADJDYNALLOC$")>;
    109 
    110 //===----------------------------------------------------------------------===//
    111 // Branch instructions
    112 //===----------------------------------------------------------------------===//
    113 
    114 // Branch
    115 def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
    116 def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Call)?J(G)?(Asm.*)?$")>;
    117 def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
    118 def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?B(R)?(Asm.*)?$")>;
    119 def : InstRW<[WLat1, FXU, EndGroup], (instregex "BRCT(G)?$")>;
    120 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCTH$")>;
    121 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;
    122 def : InstRW<[WLat1, FXU3, LSU, GroupAlone],
    123              (instregex "B(R)?X(H|L).*$")>;
    124 
    125 // Compare and branch
    126 def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>;
    127 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
    128              (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>;
    129 
    130 //===----------------------------------------------------------------------===//
    131 // Trap instructions
    132 //===----------------------------------------------------------------------===//
    133 
    134 // Trap
    135 def : InstRW<[WLat1, VBU, NormalGr], (instregex "(Cond)?Trap$")>;
    136 
    137 // Compare and trap
    138 def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(G)?(I|R)T(Asm.*)?$")>;
    139 def : InstRW<[WLat1, FXU, NormalGr], (instregex "CL(G)?RT(Asm.*)?$")>;
    140 def : InstRW<[WLat1, FXU, NormalGr], (instregex "CL(F|G)IT(Asm.*)?$")>;
    141 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
    142 
    143 //===----------------------------------------------------------------------===//
    144 // Call and return instructions
    145 //===----------------------------------------------------------------------===//
    146 
    147 // Call
    148 def : InstRW<[WLat1, FXU2, VBU, GroupAlone], (instregex "(Call)?BRAS$")>;
    149 def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BRASL$")>;
    150 def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BAS(R)?$")>;
    151 def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "TLS_(G|L)DCALL$")>;
    152 
    153 // Return
    154 def : InstRW<[WLat1, LSU, EndGroup], (instregex "Return$")>;
    155 def : InstRW<[WLat1, LSU, NormalGr], (instregex "CondReturn$")>;
    156 
    157 //===----------------------------------------------------------------------===//
    158 // Move instructions
    159 //===----------------------------------------------------------------------===//
    160 
    161 // Moves
    162 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
    163 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "MVI(Y)?$")>;
    164 
    165 // Move character
    166 def : InstRW<[WLat1, FXU, LSU3, GroupAlone], (instregex "MVC$")>;
    167 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "MVCL(E|U)?$")>;
    168 
    169 // Pseudo -> reg move
    170 def : InstRW<[WLat1, FXU, NormalGr], (instregex "COPY(_TO_REGCLASS)?$")>;
    171 def : InstRW<[WLat1, FXU, NormalGr], (instregex "EXTRACT_SUBREG$")>;
    172 def : InstRW<[WLat1, FXU, NormalGr], (instregex "INSERT_SUBREG$")>;
    173 def : InstRW<[WLat1, FXU, NormalGr], (instregex "REG_SEQUENCE$")>;
    174 
    175 // Loads
    176 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
    177 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
    178 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
    179 
    180 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLIH(F|H|L)$")>;
    181 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLIL(F|H|L)$")>;
    182 
    183 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(F|H)I$")>;
    184 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LHI(Mux)?$")>;
    185 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LR(Mux)?$")>;
    186 
    187 // Load and trap
    188 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "L(FH|G)?AT$")>;
    189 
    190 // Load and test
    191 def : InstRW<[WLat1LSU, WLat1LSU, LSU, FXU, NormalGr], (instregex "LT(G)?$")>;
    192 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LT(G)?R$")>;
    193 
    194 // Stores
    195 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STG(RL)?$")>;
    196 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST128$")>;
    197 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(Y|FH|RL|Mux)?$")>;
    198 
    199 // String moves.
    200 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "MVST$")>;
    201 
    202 //===----------------------------------------------------------------------===//
    203 // Conditional move instructions
    204 //===----------------------------------------------------------------------===//
    205 
    206 def : InstRW<[WLat2, FXU, NormalGr], (instregex "LOC(G)?R(Asm.*)?$")>;
    207 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
    208              (instregex "LOC(G)?(Asm.*)?$")>;
    209 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STOC(G)?(Asm.*)?$")>;
    210 
    211 //===----------------------------------------------------------------------===//
    212 // Sign extensions
    213 //===----------------------------------------------------------------------===//
    214 
    215 def : InstRW<[WLat1, FXU, NormalGr], (instregex "L(B|H|G)R$")>;
    216 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LG(B|H|F)R$")>;
    217 
    218 def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LTGF$")>;
    219 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LTGFR$")>;
    220 
    221 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LB(H|Mux)?$")>;
    222 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(Y)?$")>;
    223 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LH(H|Mux|RL)$")>;
    224 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LG(B|H|F)$")>;
    225 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LG(H|F)RL$")>;
    226 
    227 //===----------------------------------------------------------------------===//
    228 // Zero extensions
    229 //===----------------------------------------------------------------------===//
    230 
    231 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLCR(Mux)?$")>;
    232 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLHR(Mux)?$")>;
    233 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLG(C|H|F|T)R$")>;
    234 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLC(Mux)?$")>;
    235 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLH(Mux)?$")>;
    236 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LL(C|H)H$")>;
    237 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLHRL$")>;
    238 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLG(C|H|F|T|HRL|FRL)$")>;
    239 
    240 // Load and trap
    241 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LLG(F|T)?AT$")>;
    242 
    243 //===----------------------------------------------------------------------===//
    244 // Truncations
    245 //===----------------------------------------------------------------------===//
    246 
    247 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STC(H|Y|Mux)?$")>;
    248 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STH(H|Y|RL|Mux)?$")>;
    249 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STCM(H|Y)?$")>;
    250 
    251 //===----------------------------------------------------------------------===//
    252 // Multi-register moves
    253 //===----------------------------------------------------------------------===//
    254 
    255 // Load multiple (estimated average of 5 ops)
    256 def : InstRW<[WLat10, WLat10, LSU5, GroupAlone], (instregex "LM(H|Y|G)?$")>;
    257 
    258 // Load multiple disjoint
    259 def : InstRW<[WLat30, WLat30, MCD], (instregex "LMD$")>;
    260 
    261 // Store multiple (estimated average of 3 ops)
    262 def : InstRW<[WLat1, LSU2, FXU5, GroupAlone], (instregex "STM(H|Y|G)?$")>;
    263 
    264 //===----------------------------------------------------------------------===//
    265 // Byte swaps
    266 //===----------------------------------------------------------------------===//
    267 
    268 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LRV(G)?R$")>;
    269 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "LRV(G|H)?$")>;
    270 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STRV(G|H)?$")>;
    271 def : InstRW<[WLat30, MCD], (instregex "MVCIN$")>;
    272 
    273 //===----------------------------------------------------------------------===//
    274 // Load address instructions
    275 //===----------------------------------------------------------------------===//
    276 
    277 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LA(Y|RL)?$")>;
    278 
    279 // Load the Global Offset Table address
    280 def : InstRW<[WLat1, FXU, NormalGr], (instregex "GOT$")>;
    281 
    282 //===----------------------------------------------------------------------===//
    283 // Absolute and Negation
    284 //===----------------------------------------------------------------------===//
    285 
    286 def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "LP(G)?R$")>;
    287 def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "L(N|P)GFR$")>;
    288 def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "LN(R|GR)$")>;
    289 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LC(R|GR)$")>;
    290 def : InstRW<[WLat2, WLat2, FXU2, GroupAlone], (instregex "LCGFR$")>;
    291 
    292 //===----------------------------------------------------------------------===//
    293 // Insertion
    294 //===----------------------------------------------------------------------===//
    295 
    296 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "IC(Y)?$")>;
    297 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    298              (instregex "IC32(Y)?$")>;
    299 def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    300              (instregex "ICM(H|Y)?$")>;
    301 def : InstRW<[WLat1, FXU, NormalGr], (instregex "II(F|H|L)Mux$")>;
    302 def : InstRW<[WLat1, FXU, NormalGr], (instregex "IIHF(64)?$")>;
    303 def : InstRW<[WLat1, FXU, NormalGr], (instregex "IIHH(64)?$")>;
    304 def : InstRW<[WLat1, FXU, NormalGr], (instregex "IIHL(64)?$")>;
    305 def : InstRW<[WLat1, FXU, NormalGr], (instregex "IILF(64)?$")>;
    306 def : InstRW<[WLat1, FXU, NormalGr], (instregex "IILH(64)?$")>;
    307 def : InstRW<[WLat1, FXU, NormalGr], (instregex "IILL(64)?$")>;
    308 
    309 //===----------------------------------------------------------------------===//
    310 // Addition
    311 //===----------------------------------------------------------------------===//
    312 
    313 def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    314              (instregex "A(L)?(Y)?$")>;
    315 def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "A(L)?SI$")>;
    316 def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
    317              (instregex "AH(Y)?$")>;
    318 def : InstRW<[WLat1, FXU, NormalGr], (instregex "AIH$")>;
    319 def : InstRW<[WLat1, FXU, NormalGr], (instregex "AFI(Mux)?$")>;
    320 def : InstRW<[WLat1, FXU, NormalGr], (instregex "AGFI$")>;
    321 def : InstRW<[WLat1, FXU, NormalGr], (instregex "AGHI(K)?$")>;
    322 def : InstRW<[WLat1, FXU, NormalGr], (instregex "AGR(K)?$")>;
    323 def : InstRW<[WLat1, FXU, NormalGr], (instregex "AHI(K)?$")>;
    324 def : InstRW<[WLat1, FXU, NormalGr], (instregex "AHIMux(K)?$")>;
    325 def : InstRW<[WLat1, FXU, NormalGr], (instregex "AL(FI|HSIK)$")>;
    326 def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    327              (instregex "ALGF$")>;
    328 def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALGHSIK$")>;
    329 def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALGF(I|R)$")>;
    330 def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALGR(K)?$")>;
    331 def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALR(K)?$")>;
    332 def : InstRW<[WLat1, FXU, NormalGr], (instregex "AR(K)?$")>;
    333 def : InstRW<[WLat1, FXU, NormalGr], (instregex "A(L)?HHHR$")>;
    334 def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "A(L)?HHLR$")>;
    335 def : InstRW<[WLat1, FXU, NormalGr], (instregex "ALSIH(N)?$")>;
    336 def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    337              (instregex "A(L)?G$")>;
    338 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "A(L)?GSI$")>;
    339 
    340 // Logical addition with carry
    341 def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, GroupAlone],
    342              (instregex "ALC(G)?$")>;
    343 def : InstRW<[WLat2, WLat2, FXU, GroupAlone], (instregex "ALC(G)?R$")>;
    344 
    345 // Add with sign extension (32 -> 64)
    346 def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
    347              (instregex "AGF$")>;
    348 def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "AGFR$")>;
    349 
    350 //===----------------------------------------------------------------------===//
    351 // Subtraction
    352 //===----------------------------------------------------------------------===//
    353 
    354 def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    355              (instregex "S(G|Y)?$")>;
    356 def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
    357              (instregex "SH(Y)?$")>;
    358 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SGR(K)?$")>;
    359 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLFI$")>;
    360 def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    361              (instregex "SL(G|GF|Y)?$")>;
    362 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLGF(I|R)$")>;
    363 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLGR(K)?$")>;
    364 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLR(K)?$")>;
    365 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SR(K)?$")>;
    366 def : InstRW<[WLat1, FXU, NormalGr], (instregex "S(L)?HHHR$")>;
    367 def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "S(L)?HHLR$")>;
    368 
    369 // Subtraction with borrow
    370 def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, GroupAlone],
    371              (instregex "SLB(G)?$")>;
    372 def : InstRW<[WLat2, WLat2, FXU, GroupAlone], (instregex "SLB(G)?R$")>;
    373 
    374 // Subtraction with sign extension (32 -> 64)
    375 def : InstRW<[WLat2LSU, WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
    376              (instregex "SGF$")>;
    377 def : InstRW<[WLat2, WLat2, FXU, NormalGr], (instregex "SGFR$")>;
    378 
    379 //===----------------------------------------------------------------------===//
    380 // AND
    381 //===----------------------------------------------------------------------===//
    382 
    383 def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    384              (instregex "N(G|Y)?$")>;
    385 def : InstRW<[WLat1, FXU, NormalGr], (instregex "NGR(K)?$")>;
    386 def : InstRW<[WLat1, FXU, NormalGr], (instregex "NI(FMux|HMux|LMux)$")>;
    387 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "NI(Y)?$")>;
    388 def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIHF(64)?$")>;
    389 def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIHH(64)?$")>;
    390 def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIHL(64)?$")>;
    391 def : InstRW<[WLat1, FXU, NormalGr], (instregex "NILF(64)?$")>;
    392 def : InstRW<[WLat1, FXU, NormalGr], (instregex "NILH(64)?$")>;
    393 def : InstRW<[WLat1, FXU, NormalGr], (instregex "NILL(64)?$")>;
    394 def : InstRW<[WLat1, FXU, NormalGr], (instregex "NR(K)?$")>;
    395 def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "NC$")>;
    396 
    397 //===----------------------------------------------------------------------===//
    398 // OR
    399 //===----------------------------------------------------------------------===//
    400 
    401 def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    402              (instregex "O(G|Y)?$")>;
    403 def : InstRW<[WLat1, FXU, NormalGr], (instregex "OGR(K)?$")>;
    404 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "OI(Y)?$")>;
    405 def : InstRW<[WLat1, FXU, NormalGr], (instregex "OI(FMux|HMux|LMux)$")>;
    406 def : InstRW<[WLat1, FXU, NormalGr], (instregex "OIHF(64)?$")>;
    407 def : InstRW<[WLat1, FXU, NormalGr], (instregex "OIHH(64)?$")>;
    408 def : InstRW<[WLat1, FXU, NormalGr], (instregex "OIHL(64)?$")>;
    409 def : InstRW<[WLat1, FXU, NormalGr], (instregex "OILF(64)?$")>;
    410 def : InstRW<[WLat1, FXU, NormalGr], (instregex "OILH(64)?$")>;
    411 def : InstRW<[WLat1, FXU, NormalGr], (instregex "OILL(64)?$")>;
    412 def : InstRW<[WLat1, FXU, NormalGr], (instregex "OR(K)?$")>;
    413 def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "OC$")>;
    414 
    415 //===----------------------------------------------------------------------===//
    416 // XOR
    417 //===----------------------------------------------------------------------===//
    418 
    419 def : InstRW<[WLat1LSU, WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    420              (instregex "X(G|Y)?$")>;
    421 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "XI(Y)?$")>;
    422 def : InstRW<[WLat1, FXU, NormalGr], (instregex "XIFMux$")>;
    423 def : InstRW<[WLat1, FXU, NormalGr], (instregex "XGR(K)?$")>;
    424 def : InstRW<[WLat1, FXU, NormalGr], (instregex "XIHF(64)?$")>;
    425 def : InstRW<[WLat1, FXU, NormalGr], (instregex "XILF(64)?$")>;
    426 def : InstRW<[WLat1, FXU, NormalGr], (instregex "XR(K)?$")>;
    427 def : InstRW<[WLat5LSU, LSU2, FXU, GroupAlone], (instregex "XC$")>;
    428 
    429 //===----------------------------------------------------------------------===//
    430 // Multiplication
    431 //===----------------------------------------------------------------------===//
    432 
    433 def : InstRW<[WLat6LSU, RegReadAdv, FXU, LSU, NormalGr],
    434              (instregex "MS(GF|Y)?$")>;
    435 def : InstRW<[WLat6, FXU, NormalGr], (instregex "MS(R|FI)$")>;
    436 def : InstRW<[WLat8LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "MSG$")>;
    437 def : InstRW<[WLat8, FXU, NormalGr], (instregex "MSGR$")>;
    438 def : InstRW<[WLat6, FXU, NormalGr], (instregex "MSGF(I|R)$")>;
    439 def : InstRW<[WLat11LSU, RegReadAdv, FXU2, LSU, GroupAlone],
    440              (instregex "MLG$")>;
    441 def : InstRW<[WLat9, FXU2, GroupAlone], (instregex "MLGR$")>;
    442 def : InstRW<[WLat5, FXU, NormalGr], (instregex "MGHI$")>;
    443 def : InstRW<[WLat5, FXU, NormalGr], (instregex "MHI$")>;
    444 def : InstRW<[WLat5LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "MH(Y)?$")>;
    445 def : InstRW<[WLat7, FXU2, GroupAlone], (instregex "M(L)?R$")>;
    446 def : InstRW<[WLat7LSU, RegReadAdv, FXU2, LSU, GroupAlone],
    447              (instregex "M(FY|L)?$")>;
    448 
    449 //===----------------------------------------------------------------------===//
    450 // Division and remainder
    451 //===----------------------------------------------------------------------===//
    452 
    453 def : InstRW<[WLat30, FPU4, FXU5, GroupAlone], (instregex "DR$")>;
    454 def : InstRW<[WLat30, RegReadAdv, FPU4, LSU, FXU4, GroupAlone],
    455              (instregex "D$")>;
    456 def : InstRW<[WLat30, FPU4, FXU4, GroupAlone], (instregex "DSG(F)?R$")>;
    457 def : InstRW<[WLat30, RegReadAdv, FPU4, LSU, FXU3, GroupAlone],
    458              (instregex "DSG(F)?$")>;
    459 def : InstRW<[WLat30, FPU4, FXU5, GroupAlone], (instregex "DL(G)?R$")>;
    460 def : InstRW<[WLat30, RegReadAdv, FPU4, LSU, FXU4, GroupAlone],
    461              (instregex "DL(G)?$")>;
    462 
    463 //===----------------------------------------------------------------------===//
    464 // Shifts
    465 //===----------------------------------------------------------------------===//
    466 
    467 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLL(G|K)?$")>;
    468 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SRL(G|K)?$")>;
    469 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SRA(G|K)?$")>;
    470 def : InstRW<[WLat1, FXU, NormalGr], (instregex "SLA(G|K)?$")>;
    471 def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone],
    472              (instregex "S(L|R)D(A|L)$")>;
    473 
    474 // Rotate
    475 def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;
    476 
    477 // Rotate and insert
    478 def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?$")>;
    479 def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
    480 def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
    481 def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
    482 
    483 // Rotate and Select
    484 def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG$")>;
    485 
    486 //===----------------------------------------------------------------------===//
    487 // Comparison
    488 //===----------------------------------------------------------------------===//
    489 
    490 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "C(G|Y|Mux|RL)?$")>;
    491 def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(F|H)I(Mux)?$")>;
    492 def : InstRW<[WLat1, FXU, NormalGr], (instregex "CG(F|H)I$")>;
    493 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CG(HSI|RL)$")>;
    494 def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(G)?R$")>;
    495 def : InstRW<[WLat1, FXU, NormalGr], (instregex "CIH$")>;
    496 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CHF$")>;
    497 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CHSI$")>;
    498 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
    499              (instregex "CL(Y|Mux)?$")>;
    500 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLFHSI$")>;
    501 def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLFI(Mux)?$")>;
    502 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CLG$")>;
    503 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLG(HRL|HSI)$")>;
    504 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CLGF$")>;
    505 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLGFRL$")>;
    506 def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLGF(I|R)$")>;
    507 def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLGR$")>;
    508 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLGRL$")>;
    509 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CLHF$")>;
    510 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLH(RL|HSI)$")>;
    511 def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLIH$")>;
    512 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLI(Y)?$")>;
    513 def : InstRW<[WLat1, FXU, NormalGr], (instregex "CLR$")>;
    514 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "CLRL$")>;
    515 def : InstRW<[WLat1, FXU, NormalGr], (instregex "C(L)?HHR$")>;
    516 def : InstRW<[WLat2, FXU, NormalGr], (instregex "C(L)?HLR$")>;
    517 
    518 // Compare halfword
    519 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CH(Y)?$")>;
    520 def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "CHRL$")>;
    521 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CGH$")>;
    522 def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "CGHRL$")>;
    523 def : InstRW<[WLat2LSU, FXU2, LSU, GroupAlone], (instregex "CHHSI$")>;
    524 
    525 // Compare with sign extension (32 -> 64)
    526 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr], (instregex "CGF$")>;
    527 def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "CGFRL$")>;
    528 def : InstRW<[WLat2, FXU, NormalGr], (instregex "CGFR$")>;
    529 
    530 // Compare logical character
    531 def : InstRW<[WLat9, FXU, LSU2, GroupAlone], (instregex "CLC$")>;
    532 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CLCL(E|U)?$")>;
    533 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CLST$")>;
    534 
    535 // Test under mask
    536 def : InstRW<[WLat1LSU, FXU, LSU, NormalGr], (instregex "TM(Y)?$")>;
    537 def : InstRW<[WLat1, FXU, NormalGr], (instregex "TM(H|L)Mux$")>;
    538 def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMHH(64)?$")>;
    539 def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMHL(64)?$")>;
    540 def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMLH(64)?$")>;
    541 def : InstRW<[WLat1, FXU, NormalGr], (instregex "TMLL(64)?$")>;
    542 
    543 // Compare logical characters under mask
    544 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
    545              (instregex "CLM(H|Y)?$")>;
    546 
    547 //===----------------------------------------------------------------------===//
    548 // Prefetch and execution hint
    549 //===----------------------------------------------------------------------===//
    550 
    551 def : InstRW<[WLat1, LSU, NormalGr], (instregex "PFD(RL)?$")>;
    552 def : InstRW<[WLat1, LSU, NormalGr], (instregex "BP(R)?P$")>;
    553 def : InstRW<[WLat1, FXU, NormalGr], (instregex "NIAI$")>;
    554 
    555 //===----------------------------------------------------------------------===//
    556 // Atomic operations
    557 //===----------------------------------------------------------------------===//
    558 
    559 def : InstRW<[WLat1, LSU, EndGroup], (instregex "Serialize$")>;
    560 
    561 def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAA(G)?$")>;
    562 def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAAL(G)?$")>;
    563 def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAN(G)?$")>;
    564 def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAO(G)?$")>;
    565 def : InstRW<[WLat1LSU, WLat1LSU, FXU, LSU, NormalGr], (instregex "LAX(G)?$")>;
    566 
    567 // Test and set
    568 def : InstRW<[WLat1LSU, FXU, LSU, EndGroup], (instregex "TS$")>;
    569 
    570 // Compare and swap
    571 def : InstRW<[WLat2LSU, WLat2LSU, FXU2, LSU, GroupAlone],
    572              (instregex "CS(G|Y)?$")>;
    573 
    574 // Compare double and swap
    575 def : InstRW<[WLat5LSU, WLat5LSU, FXU5, LSU, GroupAlone],
    576              (instregex "CDS(Y)?$")>;
    577 def : InstRW<[WLat12, WLat12, FXU6, LSU2, GroupAlone],
    578              (instregex "CDSG$")>;
    579 
    580 // Compare and swap and store
    581 def : InstRW<[WLat30, MCD], (instregex "CSST$")>;
    582 
    583 // Perform locked operation
    584 def : InstRW<[WLat30, MCD], (instregex "PLO$")>;
    585 
    586 // Load/store pair from/to quadword
    587 def : InstRW<[WLat4LSU, LSU2, GroupAlone], (instregex "LPQ$")>;
    588 def : InstRW<[WLat1, FXU2, LSU2, GroupAlone], (instregex "STPQ$")>;
    589 
    590 // Load pair disjoint
    591 def : InstRW<[WLat2LSU, WLat2LSU, LSU2, GroupAlone], (instregex "LPD(G)?$")>;
    592 
    593 //===----------------------------------------------------------------------===//
    594 // Translate and convert
    595 //===----------------------------------------------------------------------===//
    596 
    597 def : InstRW<[WLat1, LSU, GroupAlone], (instregex "TR$")>;
    598 def : InstRW<[WLat30, WLat30, WLat30, FXU3, LSU2, GroupAlone],
    599              (instregex "TRT$")>;
    600 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TRTR$")>;
    601 def : InstRW<[WLat30, WLat30, MCD], (instregex "TRE$")>;
    602 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TRT(R)?E(Opt)?$")>;
    603 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "TR(T|O)(T|O)(Opt)?$")>;
    604 def : InstRW<[WLat30, WLat30, WLat30, MCD],
    605              (instregex "CU(12|14|21|24|41|42)(Opt)?$")>;
    606 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "(CUUTF|CUTFU)(Opt)?$")>;
    607 
    608 //===----------------------------------------------------------------------===//
    609 // Message-security assist
    610 //===----------------------------------------------------------------------===//
    611 
    612 def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD],
    613              (instregex "KM(C|F|O|CTR)?$")>;
    614 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "(KIMD|KLMD|KMAC|PCC)$")>;
    615 
    616 //===----------------------------------------------------------------------===//
    617 // Decimal arithmetic
    618 //===----------------------------------------------------------------------===//
    619 
    620 def : InstRW<[WLat30, RegReadAdv, FXU, DFU2, LSU2, GroupAlone],
    621              (instregex "CVBG$")>;
    622 def : InstRW<[WLat20, RegReadAdv, FXU, DFU, LSU, GroupAlone],
    623              (instregex "CVB(Y)?$")>;
    624 def : InstRW<[WLat1, FXU3, DFU4, LSU, GroupAlone], (instregex "CVDG$")>;
    625 def : InstRW<[WLat1, FXU2, DFU, LSU, GroupAlone], (instregex "CVD(Y)?$")>;
    626 def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "MV(N|O|Z)$")>;
    627 def : InstRW<[WLat1, LSU5, GroupAlone], (instregex "(PACK|PKA|PKU)$")>;
    628 def : InstRW<[WLat10, LSU5, GroupAlone], (instregex "UNPK(A|U)$")>;
    629 def : InstRW<[WLat1, FXU, LSU2, GroupAlone], (instregex "UNPK$")>;
    630 
    631 def : InstRW<[WLat11LSU, FXU, DFU4, LSU2, GroupAlone],
    632              (instregex "(A|S|ZA)P$")>;
    633 def : InstRW<[WLat1, FXU, DFU4, LSU2, GroupAlone], (instregex "(M|D)P$")>;
    634 def : InstRW<[WLat15, FXU2, DFU4, LSU3, GroupAlone], (instregex "SRP$")>;
    635 def : InstRW<[WLat11, DFU4, LSU2, GroupAlone], (instregex "CP$")>;
    636 def : InstRW<[WLat5LSU, DFU2, LSU2, GroupAlone], (instregex "TP$")>;
    637 def : InstRW<[WLat30, MCD], (instregex "ED(MK)?$")>;
    638 
    639 //===----------------------------------------------------------------------===//
    640 // Access registers
    641 //===----------------------------------------------------------------------===//
    642 
    643 // Extract/set/copy access register
    644 def : InstRW<[WLat3, LSU, NormalGr], (instregex "(EAR|SAR|CPYA)$")>;
    645 
    646 // Load address extended
    647 def : InstRW<[WLat5, LSU, FXU, GroupAlone], (instregex "LAE(Y)?$")>;
    648 
    649 // Load/store access multiple (not modeled precisely)
    650 def : InstRW<[WLat10, WLat10, LSU5, GroupAlone], (instregex "LAM(Y)?$")>;
    651 def : InstRW<[WLat1, FXU5, LSU5, GroupAlone], (instregex "STAM(Y)?$")>;
    652 
    653 //===----------------------------------------------------------------------===//
    654 // Program mask and addressing mode
    655 //===----------------------------------------------------------------------===//
    656 
    657 // Insert Program Mask
    658 def : InstRW<[WLat3, FXU, EndGroup], (instregex "IPM$")>;
    659 
    660 // Set Program Mask
    661 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
    662 
    663 // Branch and link
    664 def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "BAL(R)?$")>;
    665 
    666 // Test addressing mode
    667 def : InstRW<[WLat1, FXU, NormalGr], (instregex "TAM$")>;
    668 
    669 // Set addressing mode
    670 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
    671 
    672 // Branch (and save) and set mode.
    673 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BSM$")>;
    674 def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "BASSM$")>;
    675 
    676 //===----------------------------------------------------------------------===//
    677 // Transactional execution
    678 //===----------------------------------------------------------------------===//
    679 
    680 // Transaction begin
    681 def : InstRW<[WLat9, LSU2, FXU5, GroupAlone], (instregex "TBEGIN(C)?$")>;
    682 
    683 // Transaction end
    684 def : InstRW<[WLat4, LSU, GroupAlone], (instregex "TEND$")>;
    685 
    686 // Transaction abort
    687 def : InstRW<[WLat30, MCD], (instregex "TABORT$")>;
    688 
    689 // Extract Transaction Nesting Depth
    690 def : InstRW<[WLat30, MCD], (instregex "ETND$")>;
    691 
    692 // Nontransactional store
    693 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "NTSTG$")>;
    694 
    695 //===----------------------------------------------------------------------===//
    696 // Processor assist
    697 //===----------------------------------------------------------------------===//
    698 
    699 def : InstRW<[WLat30, MCD], (instregex "PPA$")>;
    700 
    701 //===----------------------------------------------------------------------===//
    702 // Miscellaneous Instructions.
    703 //===----------------------------------------------------------------------===//
    704 
    705 // Find leftmost one
    706 def : InstRW<[WLat7, WLat7, FXU2, GroupAlone], (instregex "FLOGR$")>;
    707 
    708 // Population count
    709 def : InstRW<[WLat3, WLat3, FXU, NormalGr], (instregex "POPCNT$")>;
    710 
    711 // String instructions
    712 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "SRST(U)?$")>;
    713 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CUSE$")>;
    714 
    715 // Various complex instructions
    716 def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "CFC$")>;
    717 def : InstRW<[WLat30, WLat30, WLat30, WLat30, WLat30, WLat30, MCD],
    718              (instregex "UPT$")>;
    719 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "CKSM$")>;
    720 def : InstRW<[WLat30, WLat30, WLat30, WLat30, MCD], (instregex "CMPSC$")>;
    721 
    722 // Execute
    723 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
    724 
    725 //===----------------------------------------------------------------------===//
    726 // .insn directive instructions
    727 //===----------------------------------------------------------------------===//
    728 
    729 // An "empty" sched-class will be assigned instead of the "invalid sched-class".
    730 // getNumDecoderSlots() will then return 1 instead of 0.
    731 def : InstRW<[], (instregex "Insn.*")>;
    732 
    733 
    734 // ----------------------------- Floating point ----------------------------- //
    735 
    736 //===----------------------------------------------------------------------===//
    737 // FP: Move instructions
    738 //===----------------------------------------------------------------------===//
    739 
    740 // Load zero
    741 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LZ(DR|ER)$")>;
    742 def : InstRW<[WLat2, FXU2, GroupAlone], (instregex "LZXR$")>;
    743 
    744 // Load
    745 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LER$")>;
    746 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LD(R|R32|GR)$")>;
    747 def : InstRW<[WLat3, FXU, NormalGr], (instregex "LGDR$")>;
    748 def : InstRW<[WLat2, FXU2, GroupAlone], (instregex "LXR$")>;
    749 
    750 // Load and Test
    751 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)BR$")>;
    752 def : InstRW<[WLat9, FPU, NormalGr], (instregex "LT(E|D)BRCompare$")>;
    753 def : InstRW<[WLat10, WLat10, FPU4, GroupAlone], (instregex "LTXBR(Compare)?$")>;
    754 
    755 // Copy sign
    756 def : InstRW<[WLat5, FXU2, GroupAlone], (instregex "CPSDR(d|s)(d|s)$")>;
    757 
    758 //===----------------------------------------------------------------------===//
    759 // FP: Load instructions
    760 //===----------------------------------------------------------------------===//
    761 
    762 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(E|D)(Y|E32)?$")>;
    763 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LX$")>;
    764 
    765 //===----------------------------------------------------------------------===//
    766 // FP: Store instructions
    767 //===----------------------------------------------------------------------===//
    768 
    769 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "ST(E|D)(Y)?$")>;
    770 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "STX$")>;
    771 
    772 //===----------------------------------------------------------------------===//
    773 // FP: Conversion instructions
    774 //===----------------------------------------------------------------------===//
    775 
    776 // Load rounded
    777 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEDBR(A)?$")>;
    778 def : InstRW<[WLat9, FPU2, NormalGr], (instregex "L(E|D)XBR(A)?$")>;
    779 
    780 // Load lengthened
    781 def : InstRW<[WLat7LSU, FPU, LSU, NormalGr], (instregex "LDEB$")>;
    782 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LDEBR$")>;
    783 def : InstRW<[WLat11LSU, FPU4, LSU, GroupAlone], (instregex "LX(E|D)B$")>;
    784 def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "LX(E|D)BR$")>;
    785 
    786 // Convert from fixed / logical
    787 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)BR(A)?$")>;
    788 def : InstRW<[WLat11, FXU, FPU4, GroupAlone], (instregex "CX(F|G)BR(A?)$")>;
    789 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CEL(F|G)BR$")>;
    790 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "CDL(F|G)BR$")>;
    791 def : InstRW<[WLat11, FXU, FPU4, GroupAlone], (instregex "CXL(F|G)BR$")>;
    792 
    793 // Convert to fixed / logical
    794 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
    795              (instregex "C(F|G)(E|D)BR(A?)$")>;
    796 def : InstRW<[WLat12, WLat12, FXU, FPU2, GroupAlone],
    797              (instregex "C(F|G)XBR(A?)$")>;
    798 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
    799              (instregex "CL(F|G)(E|D)BR$")>;
    800 def : InstRW<[WLat12, WLat12, FXU, FPU2, GroupAlone], (instregex "CL(F|G)XBR$")>;
    801 
    802 //===----------------------------------------------------------------------===//
    803 // FP: Unary arithmetic
    804 //===----------------------------------------------------------------------===//
    805 
    806 // Load Complement / Negative / Positive
    807 def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "L(C|N|P)(E|D)BR$")>;
    808 def : InstRW<[WLat1, FXU, NormalGr], (instregex "L(C|N|P)DFR(_32)?$")>;
    809 def : InstRW<[WLat10, WLat10, FPU4, GroupAlone], (instregex "L(C|N|P)XBR$")>;
    810 
    811 // Square root
    812 def : InstRW<[WLat30, FPU, LSU, NormalGr], (instregex "SQ(E|D)B$")>;
    813 def : InstRW<[WLat30, FPU, NormalGr], (instregex "SQ(E|D)BR$")>;
    814 def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "SQXBR$")>;
    815 
    816 // Load FP integer
    817 def : InstRW<[WLat7, FPU, NormalGr], (instregex "FI(E|D)BR(A)?$")>;
    818 def : InstRW<[WLat15, FPU4, GroupAlone], (instregex "FIXBR(A)?$")>;
    819 
    820 //===----------------------------------------------------------------------===//
    821 // FP: Binary arithmetic
    822 //===----------------------------------------------------------------------===//
    823 
    824 // Addition
    825 def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
    826              (instregex "A(E|D)B$")>;
    827 def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "A(E|D)BR$")>;
    828 def : InstRW<[WLat20, WLat20, FPU4, GroupAlone], (instregex "AXBR$")>;
    829 
    830 // Subtraction
    831 def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
    832              (instregex "S(E|D)B$")>;
    833 def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "S(E|D)BR$")>;
    834 def : InstRW<[WLat20, WLat20, FPU4, GroupAlone], (instregex "SXBR$")>;
    835 
    836 // Multiply
    837 def : InstRW<[WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
    838              (instregex "M(D|DE|EE)B$")>;
    839 def : InstRW<[WLat7, FPU, NormalGr], (instregex "M(D|DE|EE)BR$")>;
    840 def : InstRW<[WLat11LSU, RegReadAdv, FPU4, LSU, GroupAlone],
    841              (instregex "MXDB$")>;
    842 def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MXDBR$")>;
    843 def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "MXBR$")>;
    844 
    845 // Multiply and add / subtract
    846 def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],
    847              (instregex "M(A|S)EB$")>;
    848 def : InstRW<[WLat7, FPU, GroupAlone], (instregex "M(A|S)EBR$")>;
    849 def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],
    850              (instregex "M(A|S)DB$")>;
    851 def : InstRW<[WLat7, FPU, GroupAlone], (instregex "M(A|S)DBR$")>;
    852 
    853 // Division
    854 def : InstRW<[WLat30, RegReadAdv, FPU, LSU, NormalGr], (instregex "D(E|D)B$")>;
    855 def : InstRW<[WLat30, FPU, NormalGr], (instregex "D(E|D)BR$")>;
    856 def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "DXBR$")>;
    857 
    858 // Divide to integer
    859 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "DI(E|D)BR$")>;
    860 
    861 //===----------------------------------------------------------------------===//
    862 // FP: Comparisons
    863 //===----------------------------------------------------------------------===//
    864 
    865 // Compare
    866 def : InstRW<[WLat11LSU, RegReadAdv, FPU, LSU, NormalGr],
    867              (instregex "(K|C)(E|D)B$")>;
    868 def : InstRW<[WLat9, FPU, NormalGr], (instregex "(K|C)(E|D)BR$")>;
    869 def : InstRW<[WLat30, FPU2, NormalGr], (instregex "(K|C)XBR$")>;
    870 
    871 // Test Data Class
    872 def : InstRW<[WLat15, FPU, LSU, NormalGr], (instregex "TC(E|D)B$")>;
    873 def : InstRW<[WLat15, FPU4, LSU, GroupAlone], (instregex "TCXB$")>;
    874 
    875 //===----------------------------------------------------------------------===//
    876 // FP: Floating-point control register instructions
    877 //===----------------------------------------------------------------------===//
    878 
    879 def : InstRW<[WLat4, FXU, LSU, GroupAlone], (instregex "EFPC$")>;
    880 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "STFPC$")>;
    881 def : InstRW<[WLat1, LSU, GroupAlone], (instregex "SFPC$")>;
    882 def : InstRW<[WLat1, LSU2, GroupAlone], (instregex "LFPC$")>;
    883 def : InstRW<[WLat30, MCD], (instregex "SFASR$")>;
    884 def : InstRW<[WLat30, MCD], (instregex "LFAS$")>;
    885 def : InstRW<[WLat2, FXU, GroupAlone], (instregex "SRNM(B|T)?$")>;
    886 
    887 
    888 // --------------------- Hexadecimal floating point ------------------------- //
    889 
    890 //===----------------------------------------------------------------------===//
    891 // HFP: Move instructions
    892 //===----------------------------------------------------------------------===//
    893 
    894 // Load and Test
    895 def : InstRW<[WLat9, WLat9, FPU, NormalGr], (instregex "LT(E|D)R$")>;
    896 def : InstRW<[WLat9, WLat9, FPU4, GroupAlone], (instregex "LTXR$")>;
    897 
    898 //===----------------------------------------------------------------------===//
    899 // HFP: Conversion instructions
    900 //===----------------------------------------------------------------------===//
    901 
    902 // Load rounded
    903 def : InstRW<[WLat7, FPU, NormalGr], (instregex "(LEDR|LRER)$")>;
    904 def : InstRW<[WLat7, FPU, NormalGr], (instregex "LEXR$")>;
    905 def : InstRW<[WLat9, FPU, NormalGr], (instregex "(LDXR|LRDR)$")>;
    906 
    907 // Load lengthened
    908 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LDE$")>;
    909 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LDER$")>;
    910 def : InstRW<[WLat11LSU, FPU4, LSU, GroupAlone], (instregex "LX(E|D)$")>;
    911 def : InstRW<[WLat9, FPU4, GroupAlone], (instregex "LX(E|D)R$")>;
    912 
    913 // Convert from fixed
    914 def : InstRW<[WLat8, FXU, FPU, GroupAlone], (instregex "C(E|D)(F|G)R$")>;
    915 def : InstRW<[WLat10, FXU, FPU4, GroupAlone], (instregex "CX(F|G)R$")>;
    916 
    917 // Convert to fixed
    918 def : InstRW<[WLat12, WLat12, FXU, FPU, GroupAlone],
    919              (instregex "C(F|G)(E|D)R$")>;
    920 def : InstRW<[WLat30, WLat30, FXU, FPU2, GroupAlone], (instregex "C(F|G)XR$")>;
    921 
    922 // Convert BFP to HFP / HFP to BFP.
    923 def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "THD(E)?R$")>;
    924 def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "TB(E)?DR$")>;
    925 
    926 //===----------------------------------------------------------------------===//
    927 // HFP: Unary arithmetic
    928 //===----------------------------------------------------------------------===//
    929 
    930 // Load Complement / Negative / Positive
    931 def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "L(C|N|P)(E|D)R$")>;
    932 def : InstRW<[WLat9, WLat9, FPU4, GroupAlone], (instregex "L(C|N|P)XR$")>;
    933 
    934 // Halve
    935 def : InstRW<[WLat7, FPU, NormalGr], (instregex "H(E|D)R$")>;
    936 
    937 // Square root
    938 def : InstRW<[WLat30, FPU, LSU, NormalGr], (instregex "SQ(E|D)$")>;
    939 def : InstRW<[WLat30, FPU, NormalGr], (instregex "SQ(E|D)R$")>;
    940 def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "SQXR$")>;
    941 
    942 // Load FP integer
    943 def : InstRW<[WLat7, FPU, NormalGr], (instregex "FI(E|D)R$")>;
    944 def : InstRW<[WLat15, FPU4, GroupAlone], (instregex "FIXR$")>;
    945 
    946 //===----------------------------------------------------------------------===//
    947 // HFP: Binary arithmetic
    948 //===----------------------------------------------------------------------===//
    949 
    950 // Addition
    951 def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
    952              (instregex "A(E|D|U|W)$")>;
    953 def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "A(E|D|U|W)R$")>;
    954 def : InstRW<[WLat15, WLat15, FPU4, GroupAlone], (instregex "AXR$")>;
    955 
    956 // Subtraction
    957 def : InstRW<[WLat7LSU, WLat7LSU, RegReadAdv, FPU, LSU, NormalGr],
    958              (instregex "S(E|D|U|W)$")>;
    959 def : InstRW<[WLat7, WLat7, FPU, NormalGr], (instregex "S(E|D|U|W)R$")>;
    960 def : InstRW<[WLat15, WLat15, FPU4, GroupAlone], (instregex "SXR$")>;
    961 
    962 // Multiply
    963 def : InstRW<[WLat7LSU, RegReadAdv, FPU, LSU, NormalGr], (instregex "M(D|EE)$")>;
    964 def : InstRW<[WLat8LSU, RegReadAdv, FPU, LSU, NormalGr], (instregex "M(DE|E)$")>;
    965 def : InstRW<[WLat7, FPU, NormalGr], (instregex "M(D|EE)R$")>;
    966 def : InstRW<[WLat8, FPU, NormalGr], (instregex "M(DE|E)R$")>;
    967 def : InstRW<[WLat11LSU, RegReadAdv, FPU4, LSU, GroupAlone], (instregex "MXD$")>;
    968 def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MXDR$")>;
    969 def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "MXR$")>;
    970 def : InstRW<[WLat11LSU, RegReadAdv, FPU4, LSU, GroupAlone], (instregex "MY$")>;
    971 def : InstRW<[WLat7LSU, RegReadAdv, FPU2, LSU, GroupAlone],
    972              (instregex "MY(H|L)$")>;
    973 def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MYR$")>;
    974 def : InstRW<[WLat7, FPU, GroupAlone], (instregex "MY(H|L)R$")>;
    975 
    976 // Multiply and add / subtract
    977 def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],
    978              (instregex "M(A|S)(E|D)$")>;
    979 def : InstRW<[WLat7, FPU, GroupAlone], (instregex "M(A|S)(E|D)R$")>;
    980 def : InstRW<[WLat11LSU, RegReadAdv, RegReadAdv, FPU4, LSU, GroupAlone],
    981              (instregex "MAY$")>;
    982 def : InstRW<[WLat7LSU, RegReadAdv, RegReadAdv, FPU2, LSU, GroupAlone],
    983              (instregex "MAY(H|L)$")>;
    984 def : InstRW<[WLat10, FPU4, GroupAlone], (instregex "MAYR$")>;
    985 def : InstRW<[WLat7, FPU, GroupAlone], (instregex "MAY(H|L)R$")>;
    986 
    987 // Division
    988 def : InstRW<[WLat30, RegReadAdv, FPU, LSU, NormalGr], (instregex "D(E|D)$")>;
    989 def : InstRW<[WLat30, FPU, NormalGr], (instregex "D(E|D)R$")>;
    990 def : InstRW<[WLat30, FPU4, GroupAlone], (instregex "DXR$")>;
    991 
    992 //===----------------------------------------------------------------------===//
    993 // HFP: Comparisons
    994 //===----------------------------------------------------------------------===//
    995 
    996 // Compare
    997 def : InstRW<[WLat11LSU, RegReadAdv, FPU, LSU, NormalGr], (instregex "C(E|D)$")>;
    998 def : InstRW<[WLat9, FPU, NormalGr], (instregex "C(E|D)R$")>;
    999 def : InstRW<[WLat15, FPU2, NormalGr], (instregex "CXR$")>;
   1000 
   1001 
   1002 // ------------------------ Decimal floating point -------------------------- //
   1003 
   1004 //===----------------------------------------------------------------------===//
   1005 // DFP: Move instructions
   1006 //===----------------------------------------------------------------------===//
   1007 
   1008 // Load and Test
   1009 def : InstRW<[WLat4, WLat4, DFU, NormalGr], (instregex "LTDTR$")>;
   1010 def : InstRW<[WLat6, WLat6, DFU4, GroupAlone], (instregex "LTXTR$")>;
   1011 
   1012 //===----------------------------------------------------------------------===//
   1013 // DFP: Conversion instructions
   1014 //===----------------------------------------------------------------------===//
   1015 
   1016 // Load rounded
   1017 def : InstRW<[WLat30, DFU, NormalGr], (instregex "LEDTR$")>;
   1018 def : InstRW<[WLat30, DFU2, NormalGr], (instregex "LDXTR$")>;
   1019 
   1020 // Load lengthened
   1021 def : InstRW<[WLat7, DFU, NormalGr], (instregex "LDETR$")>;
   1022 def : InstRW<[WLat6, DFU4, GroupAlone], (instregex "LXDTR$")>;
   1023 
   1024 // Convert from fixed / logical
   1025 def : InstRW<[WLat9, FXU, DFU, GroupAlone], (instregex "CDFTR$")>;
   1026 def : InstRW<[WLat30, FXU, DFU, GroupAlone], (instregex "CDGTR(A)?$")>;
   1027 def : InstRW<[WLat5, FXU, DFU4, GroupAlone], (instregex "CXFTR(A)?$")>;
   1028 def : InstRW<[WLat30, FXU, DFU4, GroupAlone], (instregex "CXGTR(A)?$")>;
   1029 def : InstRW<[WLat9, FXU, DFU, GroupAlone], (instregex "CDL(F|G)TR$")>;
   1030 def : InstRW<[WLat9, FXU, DFU4, GroupAlone], (instregex "CXLFTR$")>;
   1031 def : InstRW<[WLat5, FXU, DFU4, GroupAlone], (instregex "CXLGTR$")>;
   1032 
   1033 // Convert to fixed / logical
   1034 def : InstRW<[WLat11, WLat11, FXU, DFU, GroupAlone], (instregex "CFDTR(A)?$")>;
   1035 def : InstRW<[WLat30, WLat30, FXU, DFU, GroupAlone], (instregex "CGDTR(A)?$")>;
   1036 def : InstRW<[WLat7, WLat7, FXU, DFU2, GroupAlone], (instregex "CFXTR$")>;
   1037 def : InstRW<[WLat30, WLat30, FXU, DFU2, GroupAlone], (instregex "CGXTR(A)?$")>;
   1038 def : InstRW<[WLat11, WLat11, FXU, DFU, GroupAlone], (instregex "CL(F|G)DTR$")>;
   1039 def : InstRW<[WLat7, WLat7, FXU, DFU2, GroupAlone], (instregex "CL(F|G)XTR$")>;
   1040 
   1041 // Convert from / to signed / unsigned packed
   1042 def : InstRW<[WLat5, FXU, DFU, GroupAlone], (instregex "CD(S|U)TR$")>;
   1043 def : InstRW<[WLat8, FXU2, DFU4, GroupAlone], (instregex "CX(S|U)TR$")>;
   1044 def : InstRW<[WLat7, FXU, DFU, GroupAlone], (instregex "C(S|U)DTR$")>;
   1045 def : InstRW<[WLat12, FXU2, DFU4, GroupAlone], (instregex "C(S|U)XTR$")>;
   1046 
   1047 // Convert from / to zoned
   1048 def : InstRW<[WLat4LSU, LSU, DFU2, GroupAlone], (instregex "CDZT$")>;
   1049 def : InstRW<[WLat11LSU, LSU2, DFU4, GroupAlone], (instregex "CXZT$")>;
   1050 def : InstRW<[WLat1, FXU, LSU, DFU2, GroupAlone], (instregex "CZDT$")>;
   1051 def : InstRW<[WLat1, FXU, LSU, DFU2, GroupAlone], (instregex "CZXT$")>;
   1052 
   1053 // Perform floating-point operation
   1054 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "PFPO$")>;
   1055 
   1056 //===----------------------------------------------------------------------===//
   1057 // DFP: Unary arithmetic
   1058 //===----------------------------------------------------------------------===//
   1059 
   1060 // Load FP integer
   1061 def : InstRW<[WLat8, DFU, NormalGr], (instregex "FIDTR$")>;
   1062 def : InstRW<[WLat10, DFU4, GroupAlone], (instregex "FIXTR$")>;
   1063 
   1064 // Extract biased exponent
   1065 def : InstRW<[WLat7, FXU, DFU, GroupAlone], (instregex "EEDTR$")>;
   1066 def : InstRW<[WLat8, FXU, DFU2, GroupAlone], (instregex "EEXTR$")>;
   1067 
   1068 // Extract significance
   1069 def : InstRW<[WLat7, FXU, DFU, GroupAlone], (instregex "ESDTR$")>;
   1070 def : InstRW<[WLat8, FXU, DFU2, GroupAlone], (instregex "ESXTR$")>;
   1071 
   1072 //===----------------------------------------------------------------------===//
   1073 // DFP: Binary arithmetic
   1074 //===----------------------------------------------------------------------===//
   1075 
   1076 // Addition
   1077 def : InstRW<[WLat9, WLat9, DFU, NormalGr], (instregex "ADTR(A)?$")>;
   1078 def : InstRW<[WLat30, WLat30, DFU4, GroupAlone], (instregex "AXTR(A)?$")>;
   1079 
   1080 // Subtraction
   1081 def : InstRW<[WLat9, WLat9, DFU, NormalGr], (instregex "SDTR(A)?$")>;
   1082 def : InstRW<[WLat30, WLat30, DFU4, GroupAlone], (instregex "SXTR(A)?$")>;
   1083 
   1084 // Multiply
   1085 def : InstRW<[WLat30, DFU, NormalGr], (instregex "MDTR(A)?$")>;
   1086 def : InstRW<[WLat30, DFU4, GroupAlone], (instregex "MXTR(A)?$")>;
   1087 
   1088 // Division
   1089 def : InstRW<[WLat30, DFU, NormalGr], (instregex "DDTR(A)?$")>;
   1090 def : InstRW<[WLat30, DFU4, GroupAlone], (instregex "DXTR(A)?$")>;
   1091 
   1092 // Quantize
   1093 def : InstRW<[WLat8, WLat8, DFU, NormalGr], (instregex "QADTR$")>;
   1094 def : InstRW<[WLat10, WLat10, DFU4, GroupAlone], (instregex "QAXTR$")>;
   1095 
   1096 // Reround
   1097 def : InstRW<[WLat11, WLat11, FXU, DFU, GroupAlone], (instregex "RRDTR$")>;
   1098 def : InstRW<[WLat30, WLat30, FXU, DFU4, GroupAlone], (instregex "RRXTR$")>;
   1099 
   1100 // Shift significand left/right
   1101 def : InstRW<[WLat7LSU, LSU, DFU, GroupAlone], (instregex "S(L|R)DT$")>;
   1102 def : InstRW<[WLat11LSU, LSU, DFU4, GroupAlone], (instregex "S(L|R)XT$")>;
   1103 
   1104 // Insert biased exponent
   1105 def : InstRW<[WLat5, FXU, DFU, GroupAlone], (instregex "IEDTR$")>;
   1106 def : InstRW<[WLat7, FXU, DFU4, GroupAlone], (instregex "IEXTR$")>;
   1107 
   1108 //===----------------------------------------------------------------------===//
   1109 // DFP: Comparisons
   1110 //===----------------------------------------------------------------------===//
   1111 
   1112 // Compare
   1113 def : InstRW<[WLat9, DFU, NormalGr], (instregex "(K|C)DTR$")>;
   1114 def : InstRW<[WLat10, DFU2, NormalGr], (instregex "(K|C)XTR$")>;
   1115 
   1116 // Compare biased exponent
   1117 def : InstRW<[WLat4, DFU, NormalGr], (instregex "CEDTR$")>;
   1118 def : InstRW<[WLat5, DFU2, NormalGr], (instregex "CEXTR$")>;
   1119 
   1120 // Test Data Class/Group
   1121 def : InstRW<[WLat9, LSU, DFU, NormalGr], (instregex "TD(C|G)DT$")>;
   1122 def : InstRW<[WLat10, LSU, DFU, NormalGr], (instregex "TD(C|G)ET$")>;
   1123 def : InstRW<[WLat10, LSU, DFU2, NormalGr], (instregex "TD(C|G)XT$")>;
   1124 
   1125 
   1126 // -------------------------------- System ---------------------------------- //
   1127 
   1128 //===----------------------------------------------------------------------===//
   1129 // System: Program-Status Word Instructions
   1130 //===----------------------------------------------------------------------===//
   1131 
   1132 def : InstRW<[WLat30, WLat30, MCD], (instregex "EPSW$")>;
   1133 def : InstRW<[WLat30, MCD], (instregex "LPSW(E)?$")>;
   1134 def : InstRW<[WLat3, FXU, GroupAlone], (instregex "IPK$")>;
   1135 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SPKA$")>;
   1136 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SSM$")>;
   1137 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "ST(N|O)SM$")>;
   1138 def : InstRW<[WLat3, FXU, NormalGr], (instregex "IAC$")>;
   1139 def : InstRW<[WLat1, LSU, EndGroup], (instregex "SAC(F)?$")>;
   1140 
   1141 //===----------------------------------------------------------------------===//
   1142 // System: Control Register Instructions
   1143 //===----------------------------------------------------------------------===//
   1144 
   1145 def : InstRW<[WLat10, WLat10, FXU, LSU, NormalGr], (instregex "LCTL(G)?$")>;
   1146 def : InstRW<[WLat1, FXU5, LSU5, GroupAlone], (instregex "STCT(L|G)$")>;
   1147 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "E(P|S)A(I)?R$")>;
   1148 def : InstRW<[WLat30, MCD], (instregex "SSA(I)?R$")>;
   1149 def : InstRW<[WLat30, MCD], (instregex "ESEA$")>;
   1150 
   1151 //===----------------------------------------------------------------------===//
   1152 // System: Prefix-Register Instructions
   1153 //===----------------------------------------------------------------------===//
   1154 
   1155 def : InstRW<[WLat30, MCD], (instregex "S(T)?PX$")>;
   1156 
   1157 //===----------------------------------------------------------------------===//
   1158 // System: Storage-Key and Real Memory Instructions
   1159 //===----------------------------------------------------------------------===//
   1160 
   1161 def : InstRW<[WLat30, MCD], (instregex "ISKE$")>;
   1162 def : InstRW<[WLat30, MCD], (instregex "IVSK$")>;
   1163 def : InstRW<[WLat30, MCD], (instregex "SSKE(Opt)?$")>;
   1164 def : InstRW<[WLat30, MCD], (instregex "RRB(E|M)$")>;
   1165 def : InstRW<[WLat30, MCD], (instregex "PFMF$")>;
   1166 def : InstRW<[WLat30, WLat30, MCD], (instregex "TB$")>;
   1167 def : InstRW<[WLat30, MCD], (instregex "PGIN$")>;
   1168 def : InstRW<[WLat30, MCD], (instregex "PGOUT$")>;
   1169 
   1170 //===----------------------------------------------------------------------===//
   1171 // System: Dynamic-Address-Translation Instructions
   1172 //===----------------------------------------------------------------------===//
   1173 
   1174 def : InstRW<[WLat30, MCD], (instregex "IPTE(Opt)?(Opt)?$")>;
   1175 def : InstRW<[WLat30, MCD], (instregex "IDTE(Opt)?$")>;
   1176 def : InstRW<[WLat30, MCD], (instregex "CRDTE(Opt)?$")>;
   1177 def : InstRW<[WLat30, MCD], (instregex "PTLB$")>;
   1178 def : InstRW<[WLat30, WLat30, MCD], (instregex "CSP(G)?$")>;
   1179 def : InstRW<[WLat30, WLat30, WLat30, MCD], (instregex "LPTEA$")>;
   1180 def : InstRW<[WLat30, WLat30, MCD], (instregex "LRA(Y|G)?$")>;
   1181 def : InstRW<[WLat30, MCD], (instregex "STRAG$")>;
   1182 def : InstRW<[WLat30, MCD], (instregex "LURA(G)?$")>;
   1183 def : InstRW<[WLat30, MCD], (instregex "STUR(A|G)$")>;
   1184 def : InstRW<[WLat30, MCD], (instregex "TPROT$")>;
   1185 
   1186 //===----------------------------------------------------------------------===//
   1187 // System: Memory-move Instructions
   1188 //===----------------------------------------------------------------------===//
   1189 
   1190 def : InstRW<[WLat30, MCD], (instregex "MVC(K|P|S)$")>;
   1191 def : InstRW<[WLat30, MCD], (instregex "MVC(S|D)K$")>;
   1192 def : InstRW<[WLat30, MCD], (instregex "MVCOS$")>;
   1193 def : InstRW<[WLat30, MCD], (instregex "MVPG$")>;
   1194 
   1195 //===----------------------------------------------------------------------===//
   1196 // System: Address-Space Instructions
   1197 //===----------------------------------------------------------------------===//
   1198 
   1199 def : InstRW<[WLat30, MCD], (instregex "LASP$")>;
   1200 def : InstRW<[WLat1, LSU, GroupAlone], (instregex "PALB$")>;
   1201 def : InstRW<[WLat30, MCD], (instregex "PC$")>;
   1202 def : InstRW<[WLat30, MCD], (instregex "PR$")>;
   1203 def : InstRW<[WLat30, MCD], (instregex "PT(I)?$")>;
   1204 def : InstRW<[WLat30, MCD], (instregex "RP$")>;
   1205 def : InstRW<[WLat30, MCD], (instregex "BS(G|A)$")>;
   1206 def : InstRW<[WLat30, MCD], (instregex "TAR$")>;
   1207 
   1208 //===----------------------------------------------------------------------===//
   1209 // System: Linkage-Stack Instructions
   1210 //===----------------------------------------------------------------------===//
   1211 
   1212 def : InstRW<[WLat30, MCD], (instregex "BAKR$")>;
   1213 def : InstRW<[WLat30, MCD], (instregex "EREG(G)?$")>;
   1214 def : InstRW<[WLat30, WLat30, MCD], (instregex "(E|M)STA$")>;
   1215 
   1216 //===----------------------------------------------------------------------===//
   1217 // System: Time-Related Instructions
   1218 //===----------------------------------------------------------------------===//
   1219 
   1220 def : InstRW<[WLat30, MCD], (instregex "PTFF$")>;
   1221 def : InstRW<[WLat30, MCD], (instregex "SCK$")>;
   1222 def : InstRW<[WLat30, MCD], (instregex "SCKPF$")>;
   1223 def : InstRW<[WLat30, MCD], (instregex "SCKC$")>;
   1224 def : InstRW<[WLat30, MCD], (instregex "SPT$")>;
   1225 def : InstRW<[WLat9, FXU, LSU2, GroupAlone], (instregex "STCK(F)?$")>;
   1226 def : InstRW<[WLat20, LSU4, FXU2, GroupAlone], (instregex "STCKE$")>;
   1227 def : InstRW<[WLat30, MCD], (instregex "STCKC$")>;
   1228 def : InstRW<[WLat30, MCD], (instregex "STPT$")>;
   1229 
   1230 //===----------------------------------------------------------------------===//
   1231 // System: CPU-Related Instructions
   1232 //===----------------------------------------------------------------------===//
   1233 
   1234 def : InstRW<[WLat30, MCD], (instregex "STAP$")>;
   1235 def : InstRW<[WLat30, MCD], (instregex "STIDP$")>;
   1236 def : InstRW<[WLat30, WLat30, MCD], (instregex "STSI$")>;
   1237 def : InstRW<[WLat30, WLat30, MCD], (instregex "STFL(E)?$")>;
   1238 def : InstRW<[WLat30, MCD], (instregex "ECAG$")>;
   1239 def : InstRW<[WLat30, WLat30, MCD], (instregex "ECTG$")>;
   1240 def : InstRW<[WLat30, MCD], (instregex "PTF$")>;
   1241 def : InstRW<[WLat30, MCD], (instregex "PCKMO$")>;
   1242 
   1243 //===----------------------------------------------------------------------===//
   1244 // System: Miscellaneous Instructions
   1245 //===----------------------------------------------------------------------===//
   1246 
   1247 def : InstRW<[WLat30, MCD], (instregex "SVC$")>;
   1248 def : InstRW<[WLat1, FXU, GroupAlone], (instregex "MC$")>;
   1249 def : InstRW<[WLat30, MCD], (instregex "DIAG$")>;
   1250 def : InstRW<[WLat1, FXU, NormalGr], (instregex "TRAC(E|G)$")>;
   1251 def : InstRW<[WLat30, MCD], (instregex "TRAP(2|4)$")>;
   1252 def : InstRW<[WLat30, MCD], (instregex "SIG(P|A)$")>;
   1253 def : InstRW<[WLat30, MCD], (instregex "SIE$")>;
   1254 
   1255 //===----------------------------------------------------------------------===//
   1256 // System: CPU-Measurement Facility Instructions
   1257 //===----------------------------------------------------------------------===//
   1258 
   1259 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LPP$")>;
   1260 def : InstRW<[WLat30, WLat30, MCD], (instregex "ECPGA$")>;
   1261 def : InstRW<[WLat30, WLat30, MCD], (instregex "E(C|P)CTR$")>;
   1262 def : InstRW<[WLat30, MCD], (instregex "LCCTL$")>;
   1263 def : InstRW<[WLat30, MCD], (instregex "L(P|S)CTL$")>;
   1264 def : InstRW<[WLat30, MCD], (instregex "Q(S|CTR)I$")>;
   1265 def : InstRW<[WLat30, MCD], (instregex "S(C|P)CTR$")>;
   1266 
   1267 //===----------------------------------------------------------------------===//
   1268 // System: I/O Instructions
   1269 //===----------------------------------------------------------------------===//
   1270 
   1271 def : InstRW<[WLat30, MCD], (instregex "(C|H|R|X)SCH$")>;
   1272 def : InstRW<[WLat30, MCD], (instregex "(M|S|ST|T)SCH$")>;
   1273 def : InstRW<[WLat30, MCD], (instregex "RCHP$")>;
   1274 def : InstRW<[WLat30, MCD], (instregex "SCHM$")>;
   1275 def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
   1276 def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
   1277 def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
   1278 
   1279 }
   1280 
   1281