1 //- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// This is a target description file for the WebAssembly architecture, 12 /// which is also known as "wasm". 13 /// 14 //===----------------------------------------------------------------------===// 15 16 //===----------------------------------------------------------------------===// 17 // Target-independent interfaces which we are implementing 18 //===----------------------------------------------------------------------===// 19 20 include "llvm/Target/Target.td" 21 22 //===----------------------------------------------------------------------===// 23 // WebAssembly Subtarget features. 24 //===----------------------------------------------------------------------===// 25 26 def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true", 27 "Enable 128-bit SIMD">; 28 def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true", 29 "Enable Atomics">; 30 def FeatureNontrappingFPToInt : 31 SubtargetFeature<"nontrapping-fptoint", 32 "HasNontrappingFPToInt", "true", 33 "Enable non-trapping float-to-int conversion operators">; 34 35 def FeatureSignExt : 36 SubtargetFeature<"sign-ext", 37 "HasSignExt", "true", 38 "Enable sign extension operators">; 39 40 def FeatureExceptionHandling : 41 SubtargetFeature<"exception-handling", "HasExceptionHandling", "true", 42 "Enable Wasm exception handling">; 43 44 //===----------------------------------------------------------------------===// 45 // Architectures. 46 //===----------------------------------------------------------------------===// 47 48 //===----------------------------------------------------------------------===// 49 // Register File Description 50 //===----------------------------------------------------------------------===// 51 52 include "WebAssemblyRegisterInfo.td" 53 54 //===----------------------------------------------------------------------===// 55 // Instruction Descriptions 56 //===----------------------------------------------------------------------===// 57 58 include "WebAssemblyInstrInfo.td" 59 60 def WebAssemblyInstrInfo : InstrInfo; 61 62 //===----------------------------------------------------------------------===// 63 // WebAssembly Processors supported. 64 //===----------------------------------------------------------------------===// 65 66 // Minimal Viable Product. 67 def : ProcessorModel<"mvp", NoSchedModel, []>; 68 69 // Generic processor: latest stable version. 70 def : ProcessorModel<"generic", NoSchedModel, []>; 71 72 // Latest and greatest experimental version of WebAssembly. Bugs included! 73 def : ProcessorModel<"bleeding-edge", NoSchedModel, 74 [FeatureSIMD128, FeatureAtomics]>; 75 76 //===----------------------------------------------------------------------===// 77 // Target Declaration 78 //===----------------------------------------------------------------------===// 79 80 def WebAssemblyAsmParser : AsmParser { 81 // The physical register names are not in the binary format or asm text 82 let ShouldEmitMatchRegisterName = 0; 83 } 84 85 def WebAssemblyAsmWriter : AsmWriter { 86 string AsmWriterClassName = "InstPrinter"; 87 int PassSubtarget = 0; 88 int Variant = 0; 89 bit isMCAsmWriter = 1; 90 } 91 92 def WebAssembly : Target { 93 let InstructionSet = WebAssemblyInstrInfo; 94 let AssemblyParsers = [WebAssemblyAsmParser]; 95 let AssemblyWriters = [WebAssemblyAsmWriter]; 96 } 97
