1 //===-- X86Instr3DNow.td - The 3DNow! Instruction Set ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the 3DNow! instruction set, which extends MMX to support 11 // floating point and also adds a few more random instructions for good measure. 12 // 13 //===----------------------------------------------------------------------===// 14 15 class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat> 16 : I<o, F, outs, ins, asm, pat>, Requires<[Has3DNow]> { 17 } 18 19 class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat> 20 : I3DNow<o, F, (outs VR64:$dst), ins, 21 !strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat>, ThreeDNow { 22 let Constraints = "$src1 = $dst"; 23 } 24 25 class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat> 26 : I3DNow<o, F, (outs VR64:$dst), ins, 27 !strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat>, ThreeDNow; 28 29 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, 30 X86FoldableSchedWrite sched, bit Commutable = 0, 31 string Ver = ""> { 32 let isCommutable = Commutable in 33 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, 34 [(set VR64:$dst, (!cast<Intrinsic>( 35 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>, 36 Sched<[sched]>; 37 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, 38 [(set VR64:$dst, (!cast<Intrinsic>( 39 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, 40 (bitconvert (load_mmx addr:$src2))))]>, 41 Sched<[sched.Folded, ReadAfterLd]>; 42 } 43 44 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, 45 X86FoldableSchedWrite sched, string Ver = ""> { 46 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn, 47 [(set VR64:$dst, (!cast<Intrinsic>( 48 !strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>, 49 Sched<[sched]>; 50 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn, 51 [(set VR64:$dst, (!cast<Intrinsic>( 52 !strconcat("int_x86_3dnow", Ver, "_", Mn)) 53 (bitconvert (load_mmx addr:$src))))]>, 54 Sched<[sched.Folded, ReadAfterLd]>; 55 } 56 57 defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb", SchedWriteVecALU.MMX, 1>; 58 defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id", WriteCvtPS2I>; 59 defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc", WriteFAdd>; 60 defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd", WriteFAdd, 1>; 61 defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq", WriteFAdd, 1>; 62 defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge", WriteFAdd>; 63 defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt", WriteFAdd>; 64 defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax", WriteFAdd>; 65 defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin", WriteFAdd>; 66 defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul", WriteFAdd, 1>; 67 defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp", WriteFAdd>; 68 defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1", WriteFAdd>; 69 defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2", WriteFAdd>; 70 defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1", WriteFAdd>; 71 defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt", WriteFAdd>; 72 defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub", WriteFAdd, 1>; 73 defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", WriteFAdd, 1>; 74 defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", WriteCvtI2PS>; 75 defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>; 76 77 let SchedRW = [WriteEMMS] in 78 def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", 79 [(int_x86_mmx_femms)]>, TB; 80 81 // PREFETCHWT1 is supported we want to use it for everything but T0. 82 def PrefetchWLevel : PatFrag<(ops), (i32 imm), [{ 83 return N->getSExtValue() == 3 || !Subtarget->hasPREFETCHWT1(); 84 }]>; 85 86 // Use PREFETCHWT1 for NTA, T2, T1. 87 def PrefetchWT1Level : ImmLeaf<i32, [{ 88 return Imm < 3; 89 }]>; 90 91 let SchedRW = [WriteLoad] in { 92 let Predicates = [Has3DNow, NoSSEPrefetch] in 93 def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr), 94 "prefetch\t$addr", 95 [(prefetch addr:$addr, imm, imm, (i32 1))]>, TB; 96 97 def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr", 98 [(prefetch addr:$addr, (i32 1), (i32 PrefetchWLevel), (i32 1))]>, 99 TB, Requires<[HasPrefetchW]>; 100 101 def PREFETCHWT1 : I<0x0D, MRM2m, (outs), (ins i8mem:$addr), "prefetchwt1\t$addr", 102 [(prefetch addr:$addr, (i32 1), (i32 PrefetchWT1Level), (i32 1))]>, 103 TB, Requires<[HasPREFETCHWT1]>; 104 } 105 106 // "3DNowA" instructions 107 defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", WriteCvtPS2I, "a">; 108 defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", WriteCvtI2PS, "a">; 109 defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", WriteFAdd, 0, "a">; 110 defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", WriteFAdd, 0, "a">; 111 defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", SchedWriteShuffle.MMX, "a">; 112
