1 //===-- X86InstrCMovSetCC.td - Conditional Move and SetCC --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 conditional move and set on condition 11 // instructions. 12 // 13 //===----------------------------------------------------------------------===// 14 15 16 // CMOV instructions. 17 multiclass CMOV<bits<8> opc, string Mnemonic, X86FoldableSchedWrite Sched, 18 PatLeaf CondNode> { 19 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", 20 isCommutable = 1, SchedRW = [Sched] in { 21 def NAME#16rr 22 : I<opc, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 23 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"), 24 [(set GR16:$dst, 25 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>, 26 TB, OpSize16; 27 def NAME#32rr 28 : I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 29 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"), 30 [(set GR32:$dst, 31 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>, 32 TB, OpSize32; 33 def NAME#64rr 34 :RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 35 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"), 36 [(set GR64:$dst, 37 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB; 38 } 39 40 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst", 41 SchedRW = [Sched.Folded, ReadAfterLd] in { 42 def NAME#16rm 43 : I<opc, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2), 44 !strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"), 45 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2), 46 CondNode, EFLAGS))]>, TB, OpSize16; 47 def NAME#32rm 48 : I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2), 49 !strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"), 50 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2), 51 CondNode, EFLAGS))]>, TB, OpSize32; 52 def NAME#64rm 53 :RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2), 54 !strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"), 55 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2), 56 CondNode, EFLAGS))]>, TB; 57 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" 58 } // end multiclass 59 60 61 // Conditional Moves. 62 defm CMOVO : CMOV<0x40, "cmovo" , WriteCMOV, X86_COND_O>; 63 defm CMOVNO : CMOV<0x41, "cmovno", WriteCMOV, X86_COND_NO>; 64 defm CMOVB : CMOV<0x42, "cmovb" , WriteCMOV, X86_COND_B>; 65 defm CMOVAE : CMOV<0x43, "cmovae", WriteCMOV, X86_COND_AE>; 66 defm CMOVE : CMOV<0x44, "cmove" , WriteCMOV, X86_COND_E>; 67 defm CMOVNE : CMOV<0x45, "cmovne", WriteCMOV, X86_COND_NE>; 68 defm CMOVBE : CMOV<0x46, "cmovbe", WriteCMOV2, X86_COND_BE>; 69 defm CMOVA : CMOV<0x47, "cmova" , WriteCMOV2, X86_COND_A>; 70 defm CMOVS : CMOV<0x48, "cmovs" , WriteCMOV, X86_COND_S>; 71 defm CMOVNS : CMOV<0x49, "cmovns", WriteCMOV, X86_COND_NS>; 72 defm CMOVP : CMOV<0x4A, "cmovp" , WriteCMOV, X86_COND_P>; 73 defm CMOVNP : CMOV<0x4B, "cmovnp", WriteCMOV, X86_COND_NP>; 74 defm CMOVL : CMOV<0x4C, "cmovl" , WriteCMOV, X86_COND_L>; 75 defm CMOVGE : CMOV<0x4D, "cmovge", WriteCMOV, X86_COND_GE>; 76 defm CMOVLE : CMOV<0x4E, "cmovle", WriteCMOV, X86_COND_LE>; 77 defm CMOVG : CMOV<0x4F, "cmovg" , WriteCMOV, X86_COND_G>; 78 79 80 // SetCC instructions. 81 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> { 82 let Uses = [EFLAGS] in { 83 def r : I<opc, MRMXr, (outs GR8:$dst), (ins), 84 !strconcat(Mnemonic, "\t$dst"), 85 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))]>, 86 TB, Sched<[WriteSETCC]>; 87 def m : I<opc, MRMXm, (outs), (ins i8mem:$dst), 88 !strconcat(Mnemonic, "\t$dst"), 89 [(store (X86setcc OpNode, EFLAGS), addr:$dst)]>, 90 TB, Sched<[WriteSETCCStore]>; 91 } // Uses = [EFLAGS] 92 } 93 94 defm SETO : SETCC<0x90, "seto", X86_COND_O>; // is overflow bit set 95 defm SETNO : SETCC<0x91, "setno", X86_COND_NO>; // is overflow bit not set 96 defm SETB : SETCC<0x92, "setb", X86_COND_B>; // unsigned less than 97 defm SETAE : SETCC<0x93, "setae", X86_COND_AE>; // unsigned greater or equal 98 defm SETE : SETCC<0x94, "sete", X86_COND_E>; // equal to 99 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to 100 defm SETBE : SETCC<0x96, "setbe", X86_COND_BE>; // unsigned less than or equal 101 defm SETA : SETCC<0x97, "seta", X86_COND_A>; // unsigned greater than 102 defm SETS : SETCC<0x98, "sets", X86_COND_S>; // is signed bit set 103 defm SETNS : SETCC<0x99, "setns", X86_COND_NS>; // is not signed 104 defm SETP : SETCC<0x9A, "setp", X86_COND_P>; // is parity bit set 105 defm SETNP : SETCC<0x9B, "setnp", X86_COND_NP>; // is parity bit not set 106 defm SETL : SETCC<0x9C, "setl", X86_COND_L>; // signed less than 107 defm SETGE : SETCC<0x9D, "setge", X86_COND_GE>; // signed greater or equal 108 defm SETLE : SETCC<0x9E, "setle", X86_COND_LE>; // signed less than or equal 109 defm SETG : SETCC<0x9F, "setg", X86_COND_G>; // signed greater than 110 111 // SALC is an undocumented instruction. Information for this instruction can be found 112 // here http://www.rcollins.org/secrets/opcodes/SALC.html 113 // Set AL if carry. 114 let Uses = [EFLAGS], Defs = [AL], SchedRW = [WriteALU] in { 115 def SALC : I<0xD6, RawFrm, (outs), (ins), "salc", []>, Requires<[Not64BitMode]>; 116 } 117
