1 //===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This describes the available hardware counters for various subtargets. 11 // 12 //===----------------------------------------------------------------------===// 13 14 let SchedModel = SandyBridgeModel in { 15 def SBCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; 16 def SBPort0Counter : PfmIssueCounter<SBPort0, ["uops_dispatched_port:port_0"]>; 17 def SBPort1Counter : PfmIssueCounter<SBPort1, ["uops_dispatched_port:port_1"]>; 18 def SBPort23Counter : PfmIssueCounter<SBPort23, 19 ["uops_dispatched_port:port_2", 20 "uops_dispatched_port:port_3"]>; 21 def SBPort4Counter : PfmIssueCounter<SBPort4, ["uops_dispatched_port:port_4"]>; 22 def SBPort5Counter : PfmIssueCounter<SBPort5, ["uops_dispatched_port:port_5"]>; 23 } 24 25 let SchedModel = HaswellModel in { 26 def HWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; 27 def HWPort0Counter : PfmIssueCounter<HWPort0, ["uops_dispatched_port:port_0"]>; 28 def HWPort1Counter : PfmIssueCounter<HWPort1, ["uops_dispatched_port:port_1"]>; 29 def HWPort2Counter : PfmIssueCounter<HWPort2, ["uops_dispatched_port:port_2"]>; 30 def HWPort3Counter : PfmIssueCounter<HWPort3, ["uops_dispatched_port:port_3"]>; 31 def HWPort4Counter : PfmIssueCounter<HWPort4, ["uops_dispatched_port:port_4"]>; 32 def HWPort5Counter : PfmIssueCounter<HWPort5, ["uops_dispatched_port:port_5"]>; 33 def HWPort6Counter : PfmIssueCounter<HWPort6, ["uops_dispatched_port:port_6"]>; 34 def HWPort7Counter : PfmIssueCounter<HWPort7, ["uops_dispatched_port:port_7"]>; 35 } 36 37 let SchedModel = BroadwellModel in { 38 def BWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; 39 def BWPort0Counter : PfmIssueCounter<BWPort0, ["uops_executed_port:port_0"]>; 40 def BWPort1Counter : PfmIssueCounter<BWPort1, ["uops_executed_port:port_1"]>; 41 def BWPort2Counter : PfmIssueCounter<BWPort2, ["uops_executed_port:port_2"]>; 42 def BWPort3Counter : PfmIssueCounter<BWPort3, ["uops_executed_port:port_3"]>; 43 def BWPort4Counter : PfmIssueCounter<BWPort4, ["uops_executed_port:port_4"]>; 44 def BWPort5Counter : PfmIssueCounter<BWPort5, ["uops_executed_port:port_5"]>; 45 def BWPort6Counter : PfmIssueCounter<BWPort6, ["uops_executed_port:port_6"]>; 46 def BWPort7Counter : PfmIssueCounter<BWPort7, ["uops_executed_port:port_7"]>; 47 } 48 49 let SchedModel = SkylakeClientModel in { 50 def SKLCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; 51 def SKLPort0Counter : PfmIssueCounter<SKLPort0, ["uops_dispatched_port:port_0"]>; 52 def SKLPort1Counter : PfmIssueCounter<SKLPort1, ["uops_dispatched_port:port_1"]>; 53 def SKLPort2Counter : PfmIssueCounter<SKLPort2, ["uops_dispatched_port:port_2"]>; 54 def SKLPort3Counter : PfmIssueCounter<SKLPort3, ["uops_dispatched_port:port_3"]>; 55 def SKLPort4Counter : PfmIssueCounter<SKLPort4, ["uops_dispatched_port:port_4"]>; 56 def SKLPort5Counter : PfmIssueCounter<SKLPort5, ["uops_dispatched_port:port_5"]>; 57 def SKLPort6Counter : PfmIssueCounter<SKLPort6, ["uops_dispatched_port:port_6"]>; 58 def SKLPort7Counter : PfmIssueCounter<SKLPort7, ["uops_dispatched_port:port_7"]>; 59 } 60 61 let SchedModel = SkylakeServerModel in { 62 def SKXCycleCounter : PfmCycleCounter<"unhalted_core_cycles">; 63 def SKXPort0Counter : PfmIssueCounter<SKXPort0, ["uops_dispatched_port:port_0"]>; 64 def SKXPort1Counter : PfmIssueCounter<SKXPort1, ["uops_dispatched_port:port_1"]>; 65 def SKXPort2Counter : PfmIssueCounter<SKXPort2, ["uops_dispatched_port:port_2"]>; 66 def SKXPort3Counter : PfmIssueCounter<SKXPort3, ["uops_dispatched_port:port_3"]>; 67 def SKXPort4Counter : PfmIssueCounter<SKXPort4, ["uops_dispatched_port:port_4"]>; 68 def SKXPort5Counter : PfmIssueCounter<SKXPort5, ["uops_dispatched_port:port_5"]>; 69 def SKXPort6Counter : PfmIssueCounter<SKXPort6, ["uops_dispatched_port:port_6"]>; 70 def SKXPort7Counter : PfmIssueCounter<SKXPort7, ["uops_dispatched_port:port_7"]>; 71 } 72 73 let SchedModel = BtVer2Model in { 74 def JCycleCounter : PfmCycleCounter<"cpu_clk_unhalted">; 75 def JFPU0Counter : PfmIssueCounter<JFPU0, ["dispatched_fpu:pipe0"]>; 76 def JFPU1Counter : PfmIssueCounter<JFPU1, ["dispatched_fpu:pipe1"]>; 77 } 78
