1 //===-- X86SchedPredicates.td - X86 Scheduling Predicates --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines scheduling predicate definitions that are common to 11 // all X86 subtargets. 12 // 13 //===----------------------------------------------------------------------===// 14 15 // A predicate used to identify dependency-breaking instructions that clear the 16 // content of the destination register. Note that this predicate only checks if 17 // input registers are the same. This predicate doesn't make any assumptions on 18 // the expected instruction opcodes, because different processors may implement 19 // different zero-idioms. 20 def ZeroIdiomPredicate : CheckSameRegOperand<1, 2>; 21 22 // A predicate used to check if an instruction is a LEA, and if it uses all 23 // three source operands: base, index, and offset. 24 def IsThreeOperandsLEAPredicate: CheckAll<[ 25 CheckOpcode<[LEA32r, LEA64r, LEA64_32r, LEA16r]>, 26 27 // isRegOperand(Base) 28 CheckIsRegOperand<1>, 29 CheckNot<CheckInvalidRegOperand<1>>, 30 31 // isRegOperand(Index) 32 CheckIsRegOperand<3>, 33 CheckNot<CheckInvalidRegOperand<3>>, 34 35 // hasLEAOffset(Offset) 36 CheckAny<[ 37 CheckAll<[ 38 CheckIsImmOperand<4>, 39 CheckNot<CheckZeroOperand<4>> 40 ]>, 41 CheckNonPortable<"MI.getOperand(4).isGlobal()"> 42 ]> 43 ]>; 44 45 // This predicate evaluates to true only if the input machine instruction is a 46 // 3-operands LEA. Tablegen automatically generates a new method for it in 47 // X86GenInstrInfo. 48 def IsThreeOperandsLEAFn : 49 TIIPredicate<"X86", "isThreeOperandsLEA", IsThreeOperandsLEAPredicate>; 50
