1 //===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the schedule class data for the Intel Atom 11 // in order (Saltwell-32nm/Bonnell-45nm) processors. 12 // 13 //===----------------------------------------------------------------------===// 14 15 // 16 // Scheduling information derived from the "Intel 64 and IA32 Architectures 17 // Optimization Reference Manual", Chapter 13, Section 4. 18 19 // Atom machine model. 20 def AtomModel : SchedMachineModel { 21 let IssueWidth = 2; // Allows 2 instructions per scheduling group. 22 let MicroOpBufferSize = 0; // In-order execution, always hide latency. 23 let LoadLatency = 3; // Expected cycles, may be overriden. 24 let HighLatency = 30;// Expected, may be overriden. 25 26 // On the Atom, the throughput for taken branches is 2 cycles. For small 27 // simple loops, expand by a small factor to hide the backedge cost. 28 let LoopMicroOpBufferSize = 10; 29 let PostRAScheduler = 1; 30 let CompleteModel = 0; 31 } 32 33 let SchedModel = AtomModel in { 34 35 // Functional Units 36 def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store 37 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide 38 def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA 39 // SIMD/FP: SIMD ALU, FP Adder 40 41 def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>; 42 43 // Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 44 // cycles after the memory operand. 45 def : ReadAdvance<ReadAfterLd, 3>; 46 47 // Many SchedWrites are defined in pairs with and without a folded load. 48 // Instructions with folded loads are usually micro-fused, so they only appear 49 // as two micro-ops when dispatched by the schedulers. 50 // This multiclass defines the resource usage for variants with and without 51 // folded loads. 52 multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW, 53 list<ProcResourceKind> RRPorts, 54 list<ProcResourceKind> RMPorts, 55 int RRLat = 1, int RMLat = 1, 56 list<int> RRRes = [1], 57 list<int> RMRes = [1]> { 58 // Register variant is using a single cycle on ExePort. 59 def : WriteRes<SchedRW, RRPorts> { 60 let Latency = RRLat; 61 let ResourceCycles = RRRes; 62 } 63 64 // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the 65 // latency. 66 def : WriteRes<SchedRW.Folded, RMPorts> { 67 let Latency = RMLat; 68 let ResourceCycles = RMRes; 69 } 70 } 71 72 // A folded store needs a cycle on Port0 for the store data. 73 def : WriteRes<WriteRMW, [AtomPort0]>; 74 75 //////////////////////////////////////////////////////////////////////////////// 76 // Arithmetic. 77 //////////////////////////////////////////////////////////////////////////////// 78 79 defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>; 80 defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>; 81 defm : AtomWriteResPair<WriteIMul, [AtomPort01], [AtomPort01], 7, 7, [7], [7]>; 82 defm : AtomWriteResPair<WriteIMul64, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>; 83 84 defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>; 85 defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>; 86 87 defm : AtomWriteResPair<WriteDiv8, [AtomPort01], [AtomPort01], 50, 68, [50], [68]>; 88 defm : AtomWriteResPair<WriteDiv16, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>; 89 defm : AtomWriteResPair<WriteDiv32, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>; 90 defm : AtomWriteResPair<WriteDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>; 91 defm : AtomWriteResPair<WriteIDiv8, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 92 defm : AtomWriteResPair<WriteIDiv16, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 93 defm : AtomWriteResPair<WriteIDiv32, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 94 defm : AtomWriteResPair<WriteIDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>; 95 96 defm : X86WriteResPairUnsupported<WriteCRC32>; 97 98 defm : AtomWriteResPair<WriteCMOV, [AtomPort01], [AtomPort0]>; 99 defm : AtomWriteResPair<WriteCMOV2, [AtomPort01], [AtomPort0]>; 100 defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move. 101 102 def : WriteRes<WriteSETCC, [AtomPort01]>; 103 def : WriteRes<WriteSETCCStore, [AtomPort01]> { 104 let Latency = 2; 105 let ResourceCycles = [2]; 106 } 107 def : WriteRes<WriteLAHFSAHF, [AtomPort01]> { 108 let Latency = 2; 109 let ResourceCycles = [2]; 110 } 111 def : WriteRes<WriteBitTest,[AtomPort01]>; 112 113 defm : X86WriteResUnsupported<WriteIMulH>; 114 115 // This is for simple LEAs with one or two input operands. 116 def : WriteRes<WriteLEA, [AtomPort1]>; 117 118 def AtomWriteIMul16Ld : SchedWriteRes<[AtomPort01]> { 119 let Latency = 8; 120 let ResourceCycles = [8]; 121 } 122 def : InstRW<[AtomWriteIMul16Ld], (instrs MUL16m, IMUL16m)>; 123 124 def AtomWriteIMul32 : SchedWriteRes<[AtomPort01]> { 125 let Latency = 6; 126 let ResourceCycles = [6]; 127 } 128 def : InstRW<[AtomWriteIMul32], (instrs MUL32r, IMUL32r)>; 129 130 def AtomWriteIMul64I : SchedWriteRes<[AtomPort01]> { 131 let Latency = 14; 132 let ResourceCycles = [14]; 133 } 134 def : InstRW<[AtomWriteIMul64I], (instrs IMUL64rri8, IMUL64rri32, 135 IMUL64rmi8, IMUL64rmi32)>; 136 137 // Bit counts. 138 defm : AtomWriteResPair<WriteBSF, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>; 139 defm : AtomWriteResPair<WriteBSR, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>; 140 defm : X86WriteResPairUnsupported<WritePOPCNT>; 141 defm : X86WriteResPairUnsupported<WriteLZCNT>; 142 defm : X86WriteResPairUnsupported<WriteTZCNT>; 143 144 // BMI1 BEXTR, BMI2 BZHI 145 defm : X86WriteResPairUnsupported<WriteBEXTR>; 146 defm : X86WriteResPairUnsupported<WriteBZHI>; 147 148 //////////////////////////////////////////////////////////////////////////////// 149 // Integer shifts and rotates. 150 //////////////////////////////////////////////////////////////////////////////// 151 152 defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>; 153 154 defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>; 155 defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>; 156 defm : X86WriteRes<WriteSHDmri, [AtomPort01], 4, [4], 1>; 157 defm : X86WriteRes<WriteSHDmrcl,[AtomPort01], 4, [4], 1>; 158 159 //////////////////////////////////////////////////////////////////////////////// 160 // Loads, stores, and moves, not folded with other operations. 161 //////////////////////////////////////////////////////////////////////////////// 162 163 def : WriteRes<WriteLoad, [AtomPort0]>; 164 def : WriteRes<WriteStore, [AtomPort0]>; 165 def : WriteRes<WriteStoreNT, [AtomPort0]>; 166 def : WriteRes<WriteMove, [AtomPort01]>; 167 168 // Treat misc copies as a move. 169 def : InstRW<[WriteMove], (instrs COPY)>; 170 171 //////////////////////////////////////////////////////////////////////////////// 172 // Idioms that clear a register, like xorps %xmm0, %xmm0. 173 // These can often bypass execution ports completely. 174 //////////////////////////////////////////////////////////////////////////////// 175 176 def : WriteRes<WriteZero, []>; 177 178 //////////////////////////////////////////////////////////////////////////////// 179 // Branches don't produce values, so they have no latency, but they still 180 // consume resources. Indirect branches can fold loads. 181 //////////////////////////////////////////////////////////////////////////////// 182 183 defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>; 184 185 //////////////////////////////////////////////////////////////////////////////// 186 // Special case scheduling classes. 187 //////////////////////////////////////////////////////////////////////////////// 188 189 def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; } 190 def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; } 191 def : WriteRes<WriteFence, [AtomPort0]>; 192 193 // Nops don't have dependencies, so there's no actual latency, but we set this 194 // to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. 195 def : WriteRes<WriteNop, [AtomPort01]>; 196 197 //////////////////////////////////////////////////////////////////////////////// 198 // Floating point. This covers both scalar and vector operations. 199 //////////////////////////////////////////////////////////////////////////////// 200 201 defm : X86WriteRes<WriteFLD0, [AtomPort01], 1, [1], 1>; 202 defm : X86WriteRes<WriteFLD1, [AtomPort01], 6, [6], 1>; 203 def : WriteRes<WriteFLoad, [AtomPort0]>; 204 def : WriteRes<WriteFLoadX, [AtomPort0]>; 205 defm : X86WriteResUnsupported<WriteFLoadY>; 206 defm : X86WriteResUnsupported<WriteFMaskedLoad>; 207 defm : X86WriteResUnsupported<WriteFMaskedLoadY>; 208 209 def : WriteRes<WriteFStore, [AtomPort0]>; 210 def : WriteRes<WriteFStoreX, [AtomPort0]>; 211 defm : X86WriteResUnsupported<WriteFStoreY>; 212 def : WriteRes<WriteFStoreNT, [AtomPort0]>; 213 def : WriteRes<WriteFStoreNTX, [AtomPort0]>; 214 defm : X86WriteResUnsupported<WriteFStoreNTY>; 215 defm : X86WriteResUnsupported<WriteFMaskedStore>; 216 defm : X86WriteResUnsupported<WriteFMaskedStoreY>; 217 218 def : WriteRes<WriteFMove, [AtomPort01]>; 219 def : WriteRes<WriteFMoveX, [AtomPort01]>; 220 defm : X86WriteResUnsupported<WriteFMoveY>; 221 222 defm : X86WriteRes<WriteEMMS, [AtomPort01], 5, [5], 1>; 223 224 defm : AtomWriteResPair<WriteFAdd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 225 defm : AtomWriteResPair<WriteFAddX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 226 defm : X86WriteResPairUnsupported<WriteFAddY>; 227 defm : X86WriteResPairUnsupported<WriteFAddZ>; 228 defm : AtomWriteResPair<WriteFAdd64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 229 defm : AtomWriteResPair<WriteFAdd64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 230 defm : X86WriteResPairUnsupported<WriteFAdd64Y>; 231 defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 232 defm : AtomWriteResPair<WriteFCmp, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 233 defm : AtomWriteResPair<WriteFCmpX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 234 defm : X86WriteResPairUnsupported<WriteFCmpY>; 235 defm : X86WriteResPairUnsupported<WriteFCmpZ>; 236 defm : AtomWriteResPair<WriteFCmp64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 237 defm : AtomWriteResPair<WriteFCmp64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 238 defm : X86WriteResPairUnsupported<WriteFCmp64Y>; 239 defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 240 defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 241 defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 242 defm : AtomWriteResPair<WriteFMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 243 defm : X86WriteResPairUnsupported<WriteFMulY>; 244 defm : X86WriteResPairUnsupported<WriteFMulZ>; 245 defm : AtomWriteResPair<WriteFMul64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 246 defm : AtomWriteResPair<WriteFMul64X, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 247 defm : X86WriteResPairUnsupported<WriteFMul64Y>; 248 defm : X86WriteResPairUnsupported<WriteFMul64Z>; 249 defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 250 defm : AtomWriteResPair<WriteFRcpX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 251 defm : X86WriteResPairUnsupported<WriteFRcpY>; 252 defm : X86WriteResPairUnsupported<WriteFRcpZ>; 253 defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 254 defm : AtomWriteResPair<WriteFRsqrtX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 255 defm : X86WriteResPairUnsupported<WriteFRsqrtY>; 256 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 257 defm : AtomWriteResPair<WriteFDiv, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>; 258 defm : AtomWriteResPair<WriteFDivX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>; 259 defm : X86WriteResPairUnsupported<WriteFDivY>; 260 defm : X86WriteResPairUnsupported<WriteFDivZ>; 261 defm : AtomWriteResPair<WriteFDiv64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 262 defm : AtomWriteResPair<WriteFDiv64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>; 263 defm : X86WriteResPairUnsupported<WriteFDiv64Y>; 264 defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 265 defm : AtomWriteResPair<WriteFSqrt, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>; 266 defm : AtomWriteResPair<WriteFSqrtX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>; 267 defm : X86WriteResPairUnsupported<WriteFSqrtY>; 268 defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 269 defm : AtomWriteResPair<WriteFSqrt64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 270 defm : AtomWriteResPair<WriteFSqrt64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>; 271 defm : X86WriteResPairUnsupported<WriteFSqrt64Y>; 272 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 273 defm : AtomWriteResPair<WriteFSqrt80, [AtomPort01], [AtomPort01], 71, 71, [71], [71]>; 274 defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>; 275 defm : AtomWriteResPair<WriteFRnd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 276 defm : X86WriteResPairUnsupported<WriteFRndY>; 277 defm : X86WriteResPairUnsupported<WriteFRndZ>; 278 defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>; 279 defm : X86WriteResPairUnsupported<WriteFLogicY>; 280 defm : X86WriteResPairUnsupported<WriteFLogicZ>; 281 defm : AtomWriteResPair<WriteFTest, [AtomPort01], [AtomPort0]>; 282 defm : X86WriteResPairUnsupported<WriteFTestY>; 283 defm : X86WriteResPairUnsupported<WriteFTestZ>; 284 defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>; 285 defm : X86WriteResPairUnsupported<WriteFShuffleY>; 286 defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 287 defm : X86WriteResPairUnsupported<WriteFVarShuffle>; 288 defm : X86WriteResPairUnsupported<WriteFVarShuffleY>; 289 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 290 defm : X86WriteResPairUnsupported<WriteFMA>; 291 defm : X86WriteResPairUnsupported<WriteFMAX>; 292 defm : X86WriteResPairUnsupported<WriteFMAY>; 293 defm : X86WriteResPairUnsupported<WriteFMAZ>; 294 defm : X86WriteResPairUnsupported<WriteDPPD>; 295 defm : X86WriteResPairUnsupported<WriteDPPS>; 296 defm : X86WriteResPairUnsupported<WriteDPPSY>; 297 defm : X86WriteResPairUnsupported<WriteDPPSZ>; 298 defm : X86WriteResPairUnsupported<WriteFBlend>; 299 defm : X86WriteResPairUnsupported<WriteFBlendY>; 300 defm : X86WriteResPairUnsupported<WriteFBlendZ>; 301 defm : X86WriteResPairUnsupported<WriteFVarBlend>; 302 defm : X86WriteResPairUnsupported<WriteFVarBlendY>; 303 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 304 defm : X86WriteResPairUnsupported<WriteFShuffle256>; 305 defm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 306 307 //////////////////////////////////////////////////////////////////////////////// 308 // Conversions. 309 //////////////////////////////////////////////////////////////////////////////// 310 311 defm : AtomWriteResPair<WriteCvtSS2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 312 defm : AtomWriteResPair<WriteCvtPS2I, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 313 defm : X86WriteResPairUnsupported<WriteCvtPS2IY>; 314 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 315 defm : AtomWriteResPair<WriteCvtSD2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 316 defm : AtomWriteResPair<WriteCvtPD2I, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 317 defm : X86WriteResPairUnsupported<WriteCvtPD2IY>; 318 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 319 320 defm : AtomWriteResPair<WriteCvtI2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 321 defm : AtomWriteResPair<WriteCvtI2PS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 322 defm : X86WriteResPairUnsupported<WriteCvtI2PSY>; 323 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 324 defm : AtomWriteResPair<WriteCvtI2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 325 defm : AtomWriteResPair<WriteCvtI2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 326 defm : X86WriteResPairUnsupported<WriteCvtI2PDY>; 327 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 328 329 defm : AtomWriteResPair<WriteCvtSS2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 330 defm : AtomWriteResPair<WriteCvtPS2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 331 defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>; 332 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 333 defm : AtomWriteResPair<WriteCvtSD2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 334 defm : AtomWriteResPair<WriteCvtPD2PS, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 335 defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>; 336 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 337 338 defm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 339 defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 340 defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 341 defm : X86WriteResUnsupported<WriteCvtPS2PH>; 342 defm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 343 defm : X86WriteResUnsupported<WriteCvtPS2PHY>; 344 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 345 defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 346 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 347 348 //////////////////////////////////////////////////////////////////////////////// 349 // Vector integer operations. 350 //////////////////////////////////////////////////////////////////////////////// 351 352 def : WriteRes<WriteVecLoad, [AtomPort0]>; 353 def : WriteRes<WriteVecLoadX, [AtomPort0]>; 354 defm : X86WriteResUnsupported<WriteVecLoadY>; 355 def : WriteRes<WriteVecLoadNT, [AtomPort0]>; 356 defm : X86WriteResUnsupported<WriteVecLoadNTY>; 357 defm : X86WriteResUnsupported<WriteVecMaskedLoad>; 358 defm : X86WriteResUnsupported<WriteVecMaskedLoadY>; 359 360 def : WriteRes<WriteVecStore, [AtomPort0]>; 361 def : WriteRes<WriteVecStoreX, [AtomPort0]>; 362 defm : X86WriteResUnsupported<WriteVecStoreY>; 363 def : WriteRes<WriteVecStoreNT, [AtomPort0]>; 364 defm : X86WriteResUnsupported<WriteVecStoreNTY>; 365 def : WriteRes<WriteVecMaskedStore, [AtomPort0]>; 366 defm : X86WriteResUnsupported<WriteVecMaskedStoreY>; 367 368 def : WriteRes<WriteVecMove, [AtomPort0]>; 369 def : WriteRes<WriteVecMoveX, [AtomPort01]>; 370 defm : X86WriteResUnsupported<WriteVecMoveY>; 371 defm : X86WriteRes<WriteVecMoveToGpr, [AtomPort0], 3, [3], 1>; 372 defm : X86WriteRes<WriteVecMoveFromGpr, [AtomPort0], 1, [1], 1>; 373 374 defm : AtomWriteResPair<WriteVecALU, [AtomPort01], [AtomPort0], 1, 1>; 375 defm : AtomWriteResPair<WriteVecALUX, [AtomPort01], [AtomPort0], 1, 1>; 376 defm : X86WriteResPairUnsupported<WriteVecALUY>; 377 defm : X86WriteResPairUnsupported<WriteVecALUZ>; 378 defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>; 379 defm : AtomWriteResPair<WriteVecLogicX, [AtomPort01], [AtomPort0], 1, 1>; 380 defm : X86WriteResPairUnsupported<WriteVecLogicY>; 381 defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 382 defm : AtomWriteResPair<WriteVecTest, [AtomPort01], [AtomPort0], 1, 1>; 383 defm : X86WriteResPairUnsupported<WriteVecTestY>; 384 defm : X86WriteResPairUnsupported<WriteVecTestZ>; 385 defm : AtomWriteResPair<WriteVecShift, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>; 386 defm : AtomWriteResPair<WriteVecShiftX, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>; 387 defm : X86WriteResPairUnsupported<WriteVecShiftY>; 388 defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 389 defm : AtomWriteResPair<WriteVecShiftImm, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>; 390 defm : AtomWriteResPair<WriteVecShiftImmX, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>; 391 defm : X86WriteResPairUnsupported<WriteVecShiftImmY>; 392 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 393 defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 394 defm : AtomWriteResPair<WriteVecIMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 395 defm : X86WriteResPairUnsupported<WriteVecIMulY>; 396 defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 397 defm : X86WriteResPairUnsupported<WritePMULLD>; 398 defm : X86WriteResPairUnsupported<WritePMULLDY>; 399 defm : X86WriteResPairUnsupported<WritePMULLDZ>; 400 defm : X86WriteResPairUnsupported<WritePHMINPOS>; 401 defm : X86WriteResPairUnsupported<WriteMPSAD>; 402 defm : X86WriteResPairUnsupported<WriteMPSADY>; 403 defm : X86WriteResPairUnsupported<WriteMPSADZ>; 404 defm : AtomWriteResPair<WritePSADBW, [AtomPort01], [AtomPort01], 4, 4, [4], [4]>; 405 defm : AtomWriteResPair<WritePSADBWX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 406 defm : X86WriteResPairUnsupported<WritePSADBWY>; 407 defm : X86WriteResPairUnsupported<WritePSADBWZ>; 408 defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>; 409 defm : AtomWriteResPair<WriteShuffleX, [AtomPort0], [AtomPort0], 1, 1>; 410 defm : X86WriteResPairUnsupported<WriteShuffleY>; 411 defm : X86WriteResPairUnsupported<WriteShuffleZ>; 412 defm : AtomWriteResPair<WriteVarShuffle, [AtomPort0], [AtomPort0], 1, 1>; 413 defm : AtomWriteResPair<WriteVarShuffleX, [AtomPort01], [AtomPort01], 4, 5, [4], [5]>; 414 defm : X86WriteResPairUnsupported<WriteVarShuffleY>; 415 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 416 defm : X86WriteResPairUnsupported<WriteBlend>; 417 defm : X86WriteResPairUnsupported<WriteBlendY>; 418 defm : X86WriteResPairUnsupported<WriteBlendZ>; 419 defm : X86WriteResPairUnsupported<WriteVarBlend>; 420 defm : X86WriteResPairUnsupported<WriteVarBlendY>; 421 defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 422 defm : X86WriteResPairUnsupported<WriteShuffle256>; 423 defm : X86WriteResPairUnsupported<WriteVarShuffle256>; 424 defm : X86WriteResPairUnsupported<WriteVarVecShift>; 425 defm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 426 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 427 428 //////////////////////////////////////////////////////////////////////////////// 429 // Vector insert/extract operations. 430 //////////////////////////////////////////////////////////////////////////////// 431 432 defm : AtomWriteResPair<WriteVecInsert, [AtomPort0], [AtomPort0], 1, 1>; 433 def : WriteRes<WriteVecExtract, [AtomPort0]>; 434 def : WriteRes<WriteVecExtractSt, [AtomPort0]>; 435 436 //////////////////////////////////////////////////////////////////////////////// 437 // SSE42 String instructions. 438 //////////////////////////////////////////////////////////////////////////////// 439 440 defm : X86WriteResPairUnsupported<WritePCmpIStrI>; 441 defm : X86WriteResPairUnsupported<WritePCmpIStrM>; 442 defm : X86WriteResPairUnsupported<WritePCmpEStrI>; 443 defm : X86WriteResPairUnsupported<WritePCmpEStrM>; 444 445 //////////////////////////////////////////////////////////////////////////////// 446 // MOVMSK Instructions. 447 //////////////////////////////////////////////////////////////////////////////// 448 449 def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 450 def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 451 defm : X86WriteResUnsupported<WriteVecMOVMSKY>; 452 def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 453 454 //////////////////////////////////////////////////////////////////////////////// 455 // AES instructions. 456 //////////////////////////////////////////////////////////////////////////////// 457 458 defm : X86WriteResPairUnsupported<WriteAESIMC>; 459 defm : X86WriteResPairUnsupported<WriteAESKeyGen>; 460 defm : X86WriteResPairUnsupported<WriteAESDecEnc>; 461 462 //////////////////////////////////////////////////////////////////////////////// 463 // Horizontal add/sub instructions. 464 //////////////////////////////////////////////////////////////////////////////// 465 466 defm : AtomWriteResPair<WriteFHAdd, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 467 defm : AtomWriteResPair<WriteFHAddY, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 468 defm : AtomWriteResPair<WritePHAdd, [AtomPort01], [AtomPort01], 3, 4, [3], [4]>; 469 defm : AtomWriteResPair<WritePHAddX, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 470 defm : AtomWriteResPair<WritePHAddY, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 471 472 //////////////////////////////////////////////////////////////////////////////// 473 // Carry-less multiplication instructions. 474 //////////////////////////////////////////////////////////////////////////////// 475 476 defm : X86WriteResPairUnsupported<WriteCLMul>; 477 478 //////////////////////////////////////////////////////////////////////////////// 479 // Load/store MXCSR. 480 //////////////////////////////////////////////////////////////////////////////// 481 482 def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; } 483 def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; } 484 485 //////////////////////////////////////////////////////////////////////////////// 486 // Special Cases. 487 //////////////////////////////////////////////////////////////////////////////// 488 489 // Port0 490 def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> { 491 let Latency = 1; 492 let ResourceCycles = [1]; 493 } 494 def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr, 495 MOVSX64rr32)>; 496 def : SchedAlias<WriteALURMW, AtomWrite0_1>; 497 def : SchedAlias<WriteADCRMW, AtomWrite0_1>; 498 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m", 499 "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>; 500 501 def AtomWrite0_5 : SchedWriteRes<[AtomPort0]> { 502 let Latency = 5; 503 let ResourceCycles = [5]; 504 } 505 def : InstRW<[AtomWrite0_5], (instregex "IMUL32(rm|rr)")>; 506 507 // Port1 508 def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> { 509 let Latency = 1; 510 let ResourceCycles = [1]; 511 } 512 def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>; 513 def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r", 514 "BT(C|R|S)?(16|32|64)(rr|ri8)")>; 515 516 def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> { 517 let Latency = 5; 518 let ResourceCycles = [5]; 519 } 520 def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm, 521 MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>; 522 523 // Port0 and Port1 524 def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> { 525 let Latency = 1; 526 let ResourceCycles = [1, 1]; 527 } 528 def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r, 529 POP16rmr, POP32rmr, POP64rmr, 530 PUSH16r, PUSH32r, PUSH64r, 531 PUSHi16, PUSHi32, 532 PUSH16rmr, PUSH32rmr, PUSH64rmr, 533 PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, 534 XCH_F)>; 535 def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$", 536 "IRET(16|32|64)?")>; 537 538 def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> { 539 let Latency = 5; 540 let ResourceCycles = [5, 5]; 541 } 542 def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>; 543 def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>; 544 545 // Port0 or Port1 546 def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> { 547 let Latency = 1; 548 let ResourceCycles = [1]; 549 } 550 def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT, 551 LFENCE, 552 STOSB, STOSL, STOSQ, STOSW, 553 MOVSSrr, MOVSSrr_REV, 554 PSLLDQri, PSRLDQri)>; 555 def : InstRW<[AtomWrite01_1], (instregex "MMX_PACK(SSDW|SSWB|USWB)irr", 556 "MMX_PUNPCKH(BW|DQ|WD)irr")>; 557 558 def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> { 559 let Latency = 2; 560 let ResourceCycles = [2]; 561 } 562 def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r, 563 PUSH16rmm, PUSH32rmm, PUSH64rmm, 564 LODSB, LODSL, LODSQ, LODSW, 565 SCASB, SCASL, SCASQ, SCASW)>; 566 def : InstRW<[AtomWrite01_2], (instregex "BT(C|R|S)(16|32|64)mi8", 567 "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)", 568 "XADD(8|16|32|64)rr", 569 "XCHG(8|16|32|64)(ar|rr)", 570 "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)", 571 "MMX_P(ADD|SUB)Qirr", 572 "MOV(S|Z)X16rr8", 573 "MOV(UPS|UPD|DQU)mr", 574 "MASKMOVDQU(64)?", 575 "P(ADD|SUB)Qrr")>; 576 577 def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> { 578 let Latency = 3; 579 let ResourceCycles = [3]; 580 } 581 def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm, 582 CMPSB, CMPSL, CMPSQ, CMPSW, 583 MOVSB, MOVSL, MOVSQ, MOVSW, 584 POP16rmm, POP32rmm, POP64rmm)>; 585 def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm", 586 "XCHG(8|16|32|64)rm", 587 "PH(ADD|SUB)Drr", 588 "MOV(S|Z)X16rm8", 589 "MMX_P(ADD|SUB)Qirm", 590 "MOV(UPS|UPD|DQU)rm", 591 "P(ADD|SUB)Qrm")>; 592 593 def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> { 594 let Latency = 4; 595 let ResourceCycles = [4]; 596 } 597 def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO, 598 JCXZ, JECXZ, JRCXZ, 599 LD_F80m)>; 600 def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm", 601 "(MMX_)?PEXTRWrr(_REV)?")>; 602 603 def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> { 604 let Latency = 5; 605 let ResourceCycles = [5]; 606 } 607 def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>; 608 def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>; 609 610 def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> { 611 let Latency = 6; 612 let ResourceCycles = [6]; 613 } 614 def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT, 615 SHLD16rrCL, SHRD16rrCL, 616 SHLD16rri8, SHRD16rri8, 617 SHLD16mrCL, SHRD16mrCL, 618 SHLD16mri8, SHRD16mri8)>; 619 def : InstRW<[AtomWrite01_6], (instregex "IMUL16rr", 620 "IST_F(P)?(16|32|64)?m", 621 "MMX_PH(ADD|SUB)S?Wrm")>; 622 623 def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> { 624 let Latency = 7; 625 let ResourceCycles = [7]; 626 } 627 def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>; 628 629 def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> { 630 let Latency = 8; 631 let ResourceCycles = [8]; 632 } 633 def : InstRW<[AtomWrite01_8], (instrs LOOPE, 634 PUSHA16, PUSHA32, 635 SHLD64rrCL, SHRD64rrCL, 636 FNSTCW16m)>; 637 638 def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> { 639 let Latency = 9; 640 let ResourceCycles = [9]; 641 } 642 def : InstRW<[AtomWrite01_9], (instrs BT16mr, BT32mr, BT64mr, 643 POPA16, POPA32, 644 PUSHF16, PUSHF32, PUSHF64, 645 SHLD64mrCL, SHRD64mrCL, 646 SHLD64mri8, SHRD64mri8, 647 SHLD64rri8, SHRD64rri8, 648 CMPXCHG8rr)>; 649 def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F", 650 "(U)?COMIS(D|S)rr", 651 "CVT(T)?SS2SI64rr(_Int)?")>; 652 653 def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> { 654 let Latency = 10; 655 let ResourceCycles = [10]; 656 } 657 def : SchedAlias<WriteFLDC, AtomWrite01_10>; 658 def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm", 659 "CVT(T)?SS2SI64rm(_Int)?")>; 660 661 def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> { 662 let Latency = 11; 663 let ResourceCycles = [11]; 664 } 665 def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>; 666 def : InstRW<[AtomWrite01_11], (instregex "BT(C|R|S)(16|32|64)mr")>; 667 668 def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> { 669 let Latency = 13; 670 let ResourceCycles = [13]; 671 } 672 def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>; 673 674 def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> { 675 let Latency = 14; 676 let ResourceCycles = [14]; 677 } 678 def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>; 679 680 def AtomWrite01_15 : SchedWriteRes<[AtomPort01]> { 681 let Latency = 15; 682 let ResourceCycles = [15]; 683 } 684 def : InstRW<[AtomWrite01_15], (instrs CMPXCHG16rr, CMPXCHG32rr, CMPXCHG64rr)>; 685 686 def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> { 687 let Latency = 17; 688 let ResourceCycles = [17]; 689 } 690 def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>; 691 692 def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> { 693 let Latency = 18; 694 let ResourceCycles = [18]; 695 } 696 def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>; 697 698 def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> { 699 let Latency = 20; 700 let ResourceCycles = [20]; 701 } 702 def : InstRW<[AtomWrite01_20], (instrs DAS)>; 703 704 def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> { 705 let Latency = 21; 706 let ResourceCycles = [21]; 707 } 708 def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>; 709 710 def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> { 711 let Latency = 22; 712 let ResourceCycles = [22]; 713 } 714 def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>; 715 716 def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> { 717 let Latency = 23; 718 let ResourceCycles = [23]; 719 } 720 def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>; 721 722 def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> { 723 let Latency = 25; 724 let ResourceCycles = [25]; 725 } 726 def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>; 727 728 def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> { 729 let Latency = 26; 730 let ResourceCycles = [26]; 731 } 732 def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>; 733 734 def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> { 735 let Latency = 29; 736 let ResourceCycles = [29]; 737 } 738 def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>; 739 740 def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> { 741 let Latency = 30; 742 let ResourceCycles = [30]; 743 } 744 def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>; 745 746 def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> { 747 let Latency = 32; 748 let ResourceCycles = [32]; 749 } 750 def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>; 751 752 def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> { 753 let Latency = 45; 754 let ResourceCycles = [45]; 755 } 756 def : InstRW<[AtomWrite01_45], (instrs MONITORrrr)>; 757 758 def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> { 759 let Latency = 46; 760 let ResourceCycles = [46]; 761 } 762 def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>; 763 764 def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> { 765 let Latency = 48; 766 let ResourceCycles = [48]; 767 } 768 def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>; 769 770 def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> { 771 let Latency = 55; 772 let ResourceCycles = [55]; 773 } 774 def : InstRW<[AtomWrite01_55], (instrs FPREM)>; 775 776 def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> { 777 let Latency = 59; 778 let ResourceCycles = [59]; 779 } 780 def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>; 781 782 def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> { 783 let Latency = 63; 784 let ResourceCycles = [63]; 785 } 786 def : InstRW<[AtomWrite01_63], (instrs FNINIT)>; 787 788 def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> { 789 let Latency = 68; 790 let ResourceCycles = [68]; 791 } 792 def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>; 793 794 def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> { 795 let Latency = 71; 796 let ResourceCycles = [71]; 797 } 798 def : InstRW<[AtomWrite01_71], (instrs FPREM1, 799 INVLPG, INVLPGA32, INVLPGA64)>; 800 801 def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> { 802 let Latency = 72; 803 let ResourceCycles = [72]; 804 } 805 def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>; 806 807 def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> { 808 let Latency = 74; 809 let ResourceCycles = [74]; 810 } 811 def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>; 812 813 def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> { 814 let Latency = 77; 815 let ResourceCycles = [77]; 816 } 817 def : InstRW<[AtomWrite01_77], (instrs FSCALE)>; 818 819 def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> { 820 let Latency = 78; 821 let ResourceCycles = [78]; 822 } 823 def : InstRW<[AtomWrite01_78], (instrs RDMSR)>; 824 825 def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> { 826 let Latency = 79; 827 let ResourceCycles = [79]; 828 } 829 def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$", 830 "LRETI?(L|Q|W)")>; 831 832 def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> { 833 let Latency = 92; 834 let ResourceCycles = [92]; 835 } 836 def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>; 837 838 def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> { 839 let Latency = 94; 840 let ResourceCycles = [94]; 841 } 842 def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>; 843 844 def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> { 845 let Latency = 99; 846 let ResourceCycles = [99]; 847 } 848 def : InstRW<[AtomWrite01_99], (instrs F2XM1)>; 849 850 def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> { 851 let Latency = 121; 852 let ResourceCycles = [121]; 853 } 854 def : InstRW<[AtomWrite01_121], (instrs CPUID)>; 855 856 def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> { 857 let Latency = 127; 858 let ResourceCycles = [127]; 859 } 860 def : InstRW<[AtomWrite01_127], (instrs INT)>; 861 862 def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> { 863 let Latency = 130; 864 let ResourceCycles = [130]; 865 } 866 def : InstRW<[AtomWrite01_130], (instrs INT3)>; 867 868 def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> { 869 let Latency = 140; 870 let ResourceCycles = [140]; 871 } 872 def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>; 873 874 def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> { 875 let Latency = 141; 876 let ResourceCycles = [141]; 877 } 878 def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>; 879 880 def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> { 881 let Latency = 146; 882 let ResourceCycles = [146]; 883 } 884 def : InstRW<[AtomWrite01_146], (instrs FYL2X)>; 885 886 def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> { 887 let Latency = 147; 888 let ResourceCycles = [147]; 889 } 890 def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>; 891 892 def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> { 893 let Latency = 168; 894 let ResourceCycles = [168]; 895 } 896 def : InstRW<[AtomWrite01_168], (instrs FPTAN)>; 897 898 def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> { 899 let Latency = 174; 900 let ResourceCycles = [174]; 901 } 902 def : InstRW<[AtomWrite01_174], (instrs FSINCOS)>; 903 def : InstRW<[AtomWrite01_174], (instregex "(COS|SIN)_F")>; 904 905 def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> { 906 let Latency = 183; 907 let ResourceCycles = [183]; 908 } 909 def : InstRW<[AtomWrite01_183], (instrs FPATAN)>; 910 911 def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> { 912 let Latency = 202; 913 let ResourceCycles = [202]; 914 } 915 def : InstRW<[AtomWrite01_202], (instrs WRMSR)>; 916 917 } // SchedModel 918
