1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s 2 3 declare <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8>, <16 x i8>) 4 5 ; CHECK-LABEL: fun1: 6 ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 7 define i32 @fun1() { 8 entry: 9 %vtbl1.i.1 = tail call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> <i8 0, i8 16, i8 19, i8 4, i8 -65, i8 -65, i8 -71, i8 -71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> undef) 10 %vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> 11 %scevgep = getelementptr <8 x i8>, <8 x i8>* undef, i64 1 12 store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1 13 ret i32 undef 14 } 15 16 ; CHECK-LABEL: fun2: 17 ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 18 define i32 @fun2() { 19 entry: 20 %vtbl1.i.1 = tail call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> <i8 0, i8 16, i8 19, i8 4, i8 -65, i8 -65, i8 -71, i8 -71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> undef) 21 %vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> 22 %scevgep = getelementptr <8 x i8>, <8 x i8>* undef, i64 1 23 store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1 24 ret i32 undef 25 } 26 27 ; CHECK-LABEL: fun3: 28 ; CHECK-NOT: uzp1 29 define i32 @fun3() { 30 entry: 31 %vtbl1.i.1 = tail call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> <i8 0, i8 16, i8 19, i8 4, i8 -65, i8 -65, i8 -71, i8 -71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> undef) 32 %vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 15> 33 %scevgep = getelementptr <8 x i8>, <8 x i8>* undef, i64 1 34 store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1 35 ret i32 undef 36 } 37 38 ; CHECK-LABEL: fun4: 39 ; CHECK-NOT: uzp2 40 define i32 @fun4() { 41 entry: 42 %vtbl1.i.1 = tail call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> <i8 0, i8 16, i8 19, i8 4, i8 -65, i8 -65, i8 -71, i8 -71, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> undef) 43 %vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 3, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> 44 %scevgep = getelementptr <8 x i8>, <8 x i8>* undef, i64 1 45 store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1 46 ret i32 undef 47 } 48 49 ; CHECK-LABEL: pr36582: 50 ; Check that this does not ICE. 51 define void @pr36582(i8* %p1, i32* %p2) { 52 entry: 53 %x = bitcast i8* %p1 to <8 x i8>* 54 %wide.vec = load <8 x i8>, <8 x i8>* %x, align 1 55 %strided.vec = shufflevector <8 x i8> %wide.vec, <8 x i8> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> 56 %y = zext <4 x i8> %strided.vec to <4 x i32> 57 %z = bitcast i32* %p2 to <4 x i32>* 58 store <4 x i32> %y, <4 x i32>* %z, align 4 59 ret void 60 } 61 62 ; Check that this pattern is recognized as a VZIP and 63 ; that the vector blend transform does not scramble the pattern. 64 ; CHECK-LABEL: vzipNoBlend: 65 ; CHECK: zip1 66 define <8 x i8> @vzipNoBlend(<8 x i8>* %A, <8 x i16>* %B) nounwind { 67 %t = load <8 x i8>, <8 x i8>* %A 68 %vzip = shufflevector <8 x i8> %t, <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef>, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> 69 ret <8 x i8> %vzip 70 } 71
