1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-NOOPT 2 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-OPT 3 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-NOOPT 4 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-OPT 5 6 define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 7 ; CHECK-LABEL: bar: 8 ; CHECK: add.2d v[[REG:[0-9]+]], v0, v1 9 ; CHECK: add d[[REG3:[0-9]+]], d[[REG]], d1 10 ; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1 11 ; CHECK-NOT: fmov 12 ; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]] 13 ; CHECK-NOT: fmov 14 ; CHECK: mov.d v0[1], [[COPY_REG2]] 15 ; CHECK-NEXT: ret 16 ; 17 ; GENERIC-LABEL: bar: 18 ; GENERIC: add v[[REG:[0-9]+]].2d, v0.2d, v1.2d 19 ; GENERIC: add d[[REG3:[0-9]+]], d[[REG]], d1 20 ; GENERIC: sub d[[REG2:[0-9]+]], d[[REG]], d1 21 ; GENERIC-NOT: fmov 22 ; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]] 23 ; GENERIC-NOT: fmov 24 ; GENERIC: mov v0.d[1], [[COPY_REG2]] 25 ; GENERIC-NEXT: ret 26 %add = add <2 x i64> %a, %b 27 %vgetq_lane = extractelement <2 x i64> %add, i32 0 28 %vgetq_lane2 = extractelement <2 x i64> %b, i32 0 29 %add3 = add i64 %vgetq_lane, %vgetq_lane2 30 %sub = sub i64 %vgetq_lane, %vgetq_lane2 31 %vecinit = insertelement <2 x i64> undef, i64 %add3, i32 0 32 %vecinit8 = insertelement <2 x i64> %vecinit, i64 %sub, i32 1 33 ret <2 x i64> %vecinit8 34 } 35 36 define double @subdd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 37 ; CHECK-LABEL: subdd_su64: 38 ; CHECK: sub d0, d1, d0 39 ; CHECK-NEXT: ret 40 ; GENERIC-LABEL: subdd_su64: 41 ; GENERIC: sub d0, d1, d0 42 ; GENERIC-NEXT: ret 43 %vecext = extractelement <2 x i64> %a, i32 0 44 %vecext1 = extractelement <2 x i64> %b, i32 0 45 %sub.i = sub nsw i64 %vecext1, %vecext 46 %retval = bitcast i64 %sub.i to double 47 ret double %retval 48 } 49 50 define double @vaddd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 51 ; CHECK-LABEL: vaddd_su64: 52 ; CHECK: add d0, d1, d0 53 ; CHECK-NEXT: ret 54 ; GENERIC-LABEL: vaddd_su64: 55 ; GENERIC: add d0, d1, d0 56 ; GENERIC-NEXT: ret 57 %vecext = extractelement <2 x i64> %a, i32 0 58 %vecext1 = extractelement <2 x i64> %b, i32 0 59 %add.i = add nsw i64 %vecext1, %vecext 60 %retval = bitcast i64 %add.i to double 61 ret double %retval 62 } 63 64 ; sub MI doesn't access dsub register. 65 define double @add_sub_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 66 ; CHECK-LABEL: add_sub_su64: 67 ; CHECK: add d0, d1, d0 68 ; CHECK: sub d0, {{d[0-9]+}}, d0 69 ; CHECK-NEXT: ret 70 ; GENERIC-LABEL: add_sub_su64: 71 ; GENERIC: add d0, d1, d0 72 ; GENERIC: sub d0, {{d[0-9]+}}, d0 73 ; GENERIC-NEXT: ret 74 %vecext = extractelement <2 x i64> %a, i32 0 75 %vecext1 = extractelement <2 x i64> %b, i32 0 76 %add.i = add i64 %vecext1, %vecext 77 %sub.i = sub i64 0, %add.i 78 %retval = bitcast i64 %sub.i to double 79 ret double %retval 80 } 81 define double @and_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 82 ; CHECK-LABEL: and_su64: 83 ; CHECK: and.8b v0, v1, v0 84 ; CHECK-NEXT: ret 85 ; GENERIC-LABEL: and_su64: 86 ; GENERIC: and v0.8b, v1.8b, v0.8b 87 ; GENERIC-NEXT: ret 88 %vecext = extractelement <2 x i64> %a, i32 0 89 %vecext1 = extractelement <2 x i64> %b, i32 0 90 %or.i = and i64 %vecext1, %vecext 91 %retval = bitcast i64 %or.i to double 92 ret double %retval 93 } 94 95 define double @orr_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 96 ; CHECK-LABEL: orr_su64: 97 ; CHECK: orr.8b v0, v1, v0 98 ; CHECK-NEXT: ret 99 ; GENERIC-LABEL: orr_su64: 100 ; GENERIC: orr v0.8b, v1.8b, v0.8b 101 ; GENERIC-NEXT: ret 102 %vecext = extractelement <2 x i64> %a, i32 0 103 %vecext1 = extractelement <2 x i64> %b, i32 0 104 %or.i = or i64 %vecext1, %vecext 105 %retval = bitcast i64 %or.i to double 106 ret double %retval 107 } 108 109 define double @xorr_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone { 110 ; CHECK-LABEL: xorr_su64: 111 ; CHECK: eor.8b v0, v1, v0 112 ; CHECK-NEXT: ret 113 ; GENERIC-LABEL: xorr_su64: 114 ; GENERIC: eor v0.8b, v1.8b, v0.8b 115 ; GENERIC-NEXT: ret 116 %vecext = extractelement <2 x i64> %a, i32 0 117 %vecext1 = extractelement <2 x i64> %b, i32 0 118 %xor.i = xor i64 %vecext1, %vecext 119 %retval = bitcast i64 %xor.i to double 120 ret double %retval 121 } 122
