1 ; RUN: llc -mtriple=arm64-linux-gnu -enable-misched=false -disable-post-ra < %s | FileCheck %s 2 3 @var = global i32 0, align 4 4 5 ; CHECK-LABEL: @test_i128_align 6 define i128 @test_i128_align(i32, i128 %arg, i32 %after) { 7 store i32 %after, i32* @var, align 4 8 ; CHECK-DAG: str w4, [{{x[0-9]+}}, :lo12:var] 9 10 ret i128 %arg 11 ; CHECK-DAG: mov x0, x2 12 ; CHECK-DAG: mov x1, x3 13 } 14 15 ; CHECK-LABEL: @test_i64x2_align 16 define [2 x i64] @test_i64x2_align(i32, [2 x i64] %arg, i32 %after) { 17 store i32 %after, i32* @var, align 4 18 ; CHECK-DAG: str w3, [{{x[0-9]+}}, :lo12:var] 19 20 ret [2 x i64] %arg 21 ; CHECK-DAG: mov x0, x1 22 ; CHECK: mov x1, x2 23 } 24 25 @var64 = global i64 0, align 8 26 27 ; Check stack slots are 64-bit at all times. 28 define void @test_stack_slots([8 x i32], i1 %bool, i8 %char, i16 %short, 29 i32 %int, i64 %long) { 30 ; CHECK-LABEL: test_stack_slots: 31 ; CHECK-DAG: ldr w[[ext1:[0-9]+]], [sp, #24] 32 ; CHECK-DAG: ldrh w[[ext2:[0-9]+]], [sp, #16] 33 ; CHECK-DAG: ldrb w[[ext3:[0-9]+]], [sp, #8] 34 ; CHECK-DAG: ldr x[[ext4:[0-9]+]], [sp, #32] 35 ; CHECK-DAG: ldrb w[[ext5:[0-9]+]], [sp] 36 ; CHECK-DAG: and x[[ext5]], x[[ext5]], #0x1 37 38 %ext_bool = zext i1 %bool to i64 39 store volatile i64 %ext_bool, i64* @var64, align 8 40 ; CHECK: str x[[ext5]], [{{x[0-9]+}}, :lo12:var64] 41 42 %ext_char = zext i8 %char to i64 43 store volatile i64 %ext_char, i64* @var64, align 8 44 ; CHECK: str x[[ext3]], [{{x[0-9]+}}, :lo12:var64] 45 46 %ext_short = zext i16 %short to i64 47 store volatile i64 %ext_short, i64* @var64, align 8 48 ; CHECK: str x[[ext2]], [{{x[0-9]+}}, :lo12:var64] 49 50 %ext_int = zext i32 %int to i64 51 store volatile i64 %ext_int, i64* @var64, align 8 52 ; CHECK: str x[[ext1]], [{{x[0-9]+}}, :lo12:var64] 53 54 store volatile i64 %long, i64* @var64, align 8 55 ; CHECK: str x[[ext4]], [{{x[0-9]+}}, :lo12:var64] 56 57 ret void 58 } 59 60 ; Make sure the callee does extensions (in the absence of zext/sext 61 ; keyword on args) while we're here. 62 63 define void @test_extension(i1 %bool, i8 %char, i16 %short, i32 %int) { 64 %ext_bool = zext i1 %bool to i64 65 store volatile i64 %ext_bool, i64* @var64 66 ; CHECK: and [[EXT:x[0-9]+]], x0, #0x1 67 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64] 68 69 %ext_char = sext i8 %char to i64 70 store volatile i64 %ext_char, i64* @var64 71 ; CHECK: sxtb [[EXT:x[0-9]+]], w1 72 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64] 73 74 %ext_short = zext i16 %short to i64 75 store volatile i64 %ext_short, i64* @var64 76 ; CHECK: and [[EXT:x[0-9]+]], x2, #0xffff 77 ; CHECK: str [[EXT]], [{{x[0-9]+}}, :lo12:var64] 78 79 %ext_int = zext i32 %int to i64 80 store volatile i64 %ext_int, i64* @var64 81 ; CHECK: mov w[[EXT:[0-9]+]], w3 82 ; CHECK: str x[[EXT]], [{{x[0-9]+}}, :lo12:var64] 83 84 ret void 85 } 86 87 declare void @variadic(i32 %a, ...) 88 89 ; Under AAPCS variadic functions have the same calling convention as 90 ; others. The extra arguments should go in registers rather than on the stack. 91 define void @test_variadic() { 92 call void(i32, ...) @variadic(i32 0, i64 1, double 2.0) 93 ; CHECK: fmov d0, #2.0 94 ; CHECK: orr w1, wzr, #0x1 95 ; CHECK: bl variadic 96 ret void 97 } 98 99 ; We weren't marking x7 as used after deciding that the i128 didn't fit into 100 ; registers and putting the first half on the stack, so the *second* half went 101 ; into x7. Yuck! 102 define i128 @test_i128_shadow([7 x i64] %x0_x6, i128 %sp) { 103 ; CHECK-LABEL: test_i128_shadow: 104 ; CHECK: ldp x0, x1, [sp] 105 106 ret i128 %sp 107 } 108 109 ; This test is to check if fp128 can be correctly handled on stack. 110 define fp128 @test_fp128([8 x float] %arg0, fp128 %arg1) { 111 ; CHECK-LABEL: test_fp128: 112 ; CHECK: ldr {{q[0-9]+}}, [sp] 113 ret fp128 %arg1 114 } 115 116 ; Check if VPR can be correctly pass by stack. 117 define <2 x double> @test_vreg_stack([8 x <2 x double>], <2 x double> %varg_stack) { 118 entry: 119 ; CHECK-LABEL: test_vreg_stack: 120 ; CHECK: ldr {{q[0-9]+}}, [sp] 121 ret <2 x double> %varg_stack; 122 } 123 124 ; Check that f16 can be passed and returned (ACLE 2.0 extension) 125 define half @test_half(float, half %arg) { 126 ; CHECK-LABEL: test_half: 127 ; CHECK: mov v0.16b, v1.16b 128 ret half %arg; 129 } 130 131 ; Check that f16 constants are materialized correctly 132 define half @test_half_const() { 133 ; CHECK-LABEL: test_half_const: 134 ; CHECK: ldr h0, [x{{[0-9]+}}, :lo12:{{.*}}] 135 ret half 0xH4248 136 } 137 138 ; Check that v4f16 can be passed and returned in registers 139 define <4 x half> @test_v4_half_register(float, <4 x half> %arg) { 140 ; CHECK-LABEL: test_v4_half_register: 141 ; CHECK: mov v0.16b, v1.16b 142 ret <4 x half> %arg; 143 } 144 145 ; Check that v8f16 can be passed and returned in registers 146 define <8 x half> @test_v8_half_register(float, <8 x half> %arg) { 147 ; CHECK-LABEL: test_v8_half_register: 148 ; CHECK: mov v0.16b, v1.16b 149 ret <8 x half> %arg; 150 } 151 152 ; Check that v4f16 can be passed and returned on the stack 153 define <4 x half> @test_v4_half_stack([8 x <2 x double>], <4 x half> %arg) { 154 ; CHECK-LABEL: test_v4_half_stack: 155 ; CHECK: ldr d0, [sp] 156 ret <4 x half> %arg; 157 } 158 159 ; Check that v8f16 can be passed and returned on the stack 160 define <8 x half> @test_v8_half_stack([8 x <2 x double>], <8 x half> %arg) { 161 ; CHECK-LABEL: test_v8_half_stack: 162 ; CHECK: ldr q0, [sp] 163 ret <8 x half> %arg; 164 } 165
