1 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s 2 3 4 define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) { 5 ; CHECK: fptosi_v4f64_to_v4i16 6 ; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d 7 ; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d 8 ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d 9 ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d 10 ; CHECK: xtn v0.4h, v[[MID]].4s 11 %tmp1 = load <4 x double>, <4 x double>* %ptr 12 %tmp2 = fptosi <4 x double> %tmp1 to <4 x i16> 13 ret <4 x i16> %tmp2 14 } 15 16 define <8 x i8> @fptosi_v4f64_to_v4i8(<8 x double>* %ptr) { 17 ; CHECK: fptosi_v4f64_to_v4i8 18 ; CHECK-DAG: fcvtzs v[[CONV0:[0-9]+]].2d, v0.2d 19 ; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d 20 ; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d 21 ; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d 22 ; CHECK-DAG: xtn v[[NA2:[0-9]+]].2s, v[[CONV2]].2d 23 ; CHECK-DAG: xtn2 v[[NA2]].4s, v[[CONV3]].2d 24 ; CHECK-DAG: xtn v[[NA0:[0-9]+]].2s, v[[CONV0]].2d 25 ; CHECK-DAG: xtn2 v[[NA0]].4s, v[[CONV1]].2d 26 ; CHECK-DAG: xtn v[[TMP1:[0-9]+]].4h, v[[NA2]].4s 27 ; CHECK-DAG: xtn2 v[[TMP1]].8h, v[[NA0]].4s 28 ; CHECK: xtn v0.8b, v[[TMP1]].8h 29 %tmp1 = load <8 x double>, <8 x double>* %ptr 30 %tmp2 = fptosi <8 x double> %tmp1 to <8 x i8> 31 ret <8 x i8> %tmp2 32 } 33 34 define <4 x half> @uitofp_v4i64_to_v4f16(<4 x i64>* %ptr) { 35 ; CHECK: uitofp_v4i64_to_v4f16 36 ; CHECK-DAG: ucvtf v[[LHS:[0-9]+]].2d, v0.2d 37 ; CHECK-DAG: ucvtf v[[RHS:[0-9]+]].2d, v1.2d 38 ; CHECK-DAG: fcvtn v[[MID:[0-9]+]].2s, v[[LHS]].2d 39 ; CHECK-DAG: fcvtn2 v[[MID]].4s, v[[RHS]].2d 40 ; CHECK: fcvtn v0.4h, v[[MID]].4s 41 %tmp1 = load <4 x i64>, <4 x i64>* %ptr 42 %tmp2 = uitofp <4 x i64> %tmp1 to <4 x half> 43 ret <4 x half> %tmp2 44 } 45 46 define <4 x i16> @trunc_v4i64_to_v4i16(<4 x i64>* %ptr) { 47 ; CHECK: trunc_v4i64_to_v4i16 48 ; CHECK: xtn 49 ; CHECK: xtn2 50 ; CHECK: xtn 51 %tmp1 = load <4 x i64>, <4 x i64>* %ptr 52 %tmp2 = trunc <4 x i64> %tmp1 to <4 x i16> 53 ret <4 x i16> %tmp2 54 } 55 56 define <4 x i16> @fptoui_v4f64_to_v4i16(<4 x double>* %ptr) { 57 ; CHECK: fptoui_v4f64_to_v4i16 58 ; CHECK-DAG: fcvtzu v[[LHS:[0-9]+]].2d, v0.2d 59 ; CHECK-DAG: fcvtzu v[[RHS:[0-9]+]].2d, v1.2d 60 ; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d 61 ; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d 62 ; CHECK: xtn v0.4h, v[[MID]].4s 63 %tmp1 = load <4 x double>, <4 x double>* %ptr 64 %tmp2 = fptoui <4 x double> %tmp1 to <4 x i16> 65 ret <4 x i16> %tmp2 66 } 67
