1 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s -mcpu=cyclone | FileCheck %s 2 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s -O0 -fast-isel -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST 3 ; RUN: llc -mtriple=arm64-linux-gnu -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-PIC 4 ; RUN: llc -mtriple=arm64-linux-gnu -O0 -fast-isel -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST-PIC 5 ; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -o - %s -mcpu=cyclone | FileCheck %s 6 ; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -o - %s -O0 -fast-isel -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST 7 ; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-PIC 8 ; RUN: llc -mtriple=aarch64-fuchsia -code-model=kernel -O0 -fast-isel -relocation-model=pic -o - %s -mcpu=cyclone | FileCheck %s --check-prefix=CHECK-FAST-PIC 9 10 @var8 = external global i8, align 1 11 @var16 = external global i16, align 2 12 @var32 = external global i32, align 4 13 @var64 = external global i64, align 8 14 15 define i8 @test_i8(i8 %new) { 16 %val = load i8, i8* @var8, align 1 17 store i8 %new, i8* @var8 18 ret i8 %val 19 ; CHECK-LABEL: test_i8: 20 ; CHECK: adrp x[[HIREG:[0-9]+]], var8 21 ; CHECK: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8] 22 ; CHECK: strb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8] 23 24 ; CHECK-PIC-LABEL: test_i8: 25 ; CHECK-PIC: adrp x[[HIREG:[0-9]+]], :got:var8 26 ; CHECK-PIC: ldr x[[VAR_ADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8] 27 ; CHECK-PIC: ldrb {{w[0-9]+}}, [x[[VAR_ADDR]]] 28 29 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var8 30 ; CHECK-FAST: ldrb {{w[0-9]+}}, [x[[HIREG]], :lo12:var8] 31 32 ; CHECK-FAST-PIC: adrp x[[HIREG:[0-9]+]], :got:var8 33 ; CHECK-FAST-PIC: ldr x[[VARADDR:[0-9]+]], [x[[HIREG]], :got_lo12:var8] 34 ; CHECK-FAST-PIC: ldr {{w[0-9]+}}, [x[[VARADDR]]] 35 } 36 37 define i16 @test_i16(i16 %new) { 38 %val = load i16, i16* @var16, align 2 39 store i16 %new, i16* @var16 40 ret i16 %val 41 ; CHECK-LABEL: test_i16: 42 ; CHECK: adrp x[[HIREG:[0-9]+]], var16 43 ; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16] 44 ; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16] 45 46 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var16 47 ; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16] 48 } 49 50 define i32 @test_i32(i32 %new) { 51 %val = load i32, i32* @var32, align 4 52 store i32 %new, i32* @var32 53 ret i32 %val 54 ; CHECK-LABEL: test_i32: 55 ; CHECK: adrp x[[HIREG:[0-9]+]], var32 56 ; CHECK: ldr {{w[0-9]+}}, [x[[HIREG]], :lo12:var32] 57 ; CHECK: str {{w[0-9]+}}, [x[[HIREG]], :lo12:var32] 58 59 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var32 60 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var32 61 } 62 63 define i64 @test_i64(i64 %new) { 64 %val = load i64, i64* @var64, align 8 65 store i64 %new, i64* @var64 66 ret i64 %val 67 ; CHECK-LABEL: test_i64: 68 ; CHECK: adrp x[[HIREG:[0-9]+]], var64 69 ; CHECK: ldr {{x[0-9]+}}, [x[[HIREG]], :lo12:var64] 70 ; CHECK: str {{x[0-9]+}}, [x[[HIREG]], :lo12:var64] 71 72 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var64 73 ; CHECK-FAST: add {{x[0-9]+}}, x[[HIREG]], :lo12:var64 74 } 75 76 define i64* @test_addr() { 77 ret i64* @var64 78 ; CHECK-LABEL: test_addr: 79 ; CHECK: adrp [[HIREG:x[0-9]+]], var64 80 ; CHECK: add x0, [[HIREG]], :lo12:var64 81 82 ; CHECK-FAST: adrp [[HIREG:x[0-9]+]], var64 83 ; CHECK-FAST: add x0, [[HIREG]], :lo12:var64 84 } 85 86 @hiddenvar = hidden global i32 0, align 4 87 @protectedvar = protected global i32 0, align 4 88 89 define i32 @test_vis() { 90 %lhs = load i32, i32* @hiddenvar, align 4 91 %rhs = load i32, i32* @protectedvar, align 4 92 %ret = add i32 %lhs, %rhs 93 ret i32 %ret 94 ; CHECK-PIC: adrp {{x[0-9]+}}, hiddenvar 95 ; CHECK-PIC: ldr {{w[0-9]+}}, [{{x[0-9]+}}, :lo12:hiddenvar] 96 ; CHECK-PIC: adrp {{x[0-9]+}}, protectedvar 97 ; CHECK-PIC: ldr {{w[0-9]+}}, [{{x[0-9]+}}, :lo12:protectedvar] 98 } 99 100 @var_default = external global [2 x i32] 101 102 define i32 @test_default_align() { 103 %addr = getelementptr [2 x i32], [2 x i32]* @var_default, i32 0, i32 0 104 %val = load i32, i32* %addr 105 ret i32 %val 106 ; CHECK-LABEL: test_default_align: 107 ; CHECK: adrp x[[HIREG:[0-9]+]], var_default 108 ; CHECK: ldr w0, [x[[HIREG]], :lo12:var_default] 109 } 110 111 define i64 @test_default_unaligned() { 112 %addr = bitcast [2 x i32]* @var_default to i64* 113 %val = load i64, i64* %addr 114 ret i64 %val 115 ; CHECK-LABEL: test_default_unaligned: 116 ; CHECK: adrp [[HIREG:x[0-9]+]], var_default 117 ; CHECK: add x[[ADDR:[0-9]+]], [[HIREG]], :lo12:var_default 118 ; CHECK: ldr x0, [x[[ADDR]]] 119 } 120
