1 ; REQUIRES: asserts 2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s 3 ; 4 ; Test for bug in misched memory dependency calculation. 5 ; 6 ; CHECK: ********** MI Scheduling ********** 7 ; CHECK: misched_bug:%bb.0 entry 8 ; CHECK: SU(2): %2:gpr32 = LDRWui %0:gpr64common, 1 :: (load 4 from %ir.ptr1_plus1) 9 ; CHECK: Successors: 10 ; CHECK-NEXT: SU(5): Data Latency=4 Reg=%2 11 ; CHECK-NEXT: SU(4): Ord Latency=0 12 ; CHECK: SU(3): STRWui $wzr, %0:gpr64common, 0 :: (store 4 into %ir.ptr1) 13 ; CHECK: Successors: 14 ; CHECK: SU(4): Ord Latency=0 15 ; CHECK: SU(4): STRWui $wzr, %1:gpr64common, 0 :: (store 4 into %ir.ptr2) 16 ; CHECK: SU(5): $w0 = COPY %2 17 ; CHECK: ** ScheduleDAGMI::schedule picking next node 18 define i32 @misched_bug(i32* %ptr1, i32* %ptr2) { 19 entry: 20 %ptr1_plus1 = getelementptr inbounds i32, i32* %ptr1, i64 1 21 %val1 = load i32, i32* %ptr1_plus1, align 4 22 store i32 0, i32* %ptr1, align 4 23 store i32 0, i32* %ptr2, align 4 24 ret i32 %val1 25 } 26
