1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s 2 3 define <16 x i8> @div16xi8(<16 x i8> %x) { 4 ; CHECK-LABEL: div16xi8: 5 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #41 6 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b 7 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b 8 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).16b]], [[SMULL]].16b, [[SMULL2]].16b 9 ; CHECK-NEXT: sshr [[SSHR:(v[0-9]+.16b)]], [[UZP2]], #2 10 ; CHECK-NEXT: usra v0.16b, [[SSHR]], #7 11 %div = sdiv <16 x i8> %x, <i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25, i8 25> 12 ret <16 x i8> %div 13 } 14 15 define <8 x i16> @div8xi16(<8 x i16> %x) { 16 ; CHECK-LABEL: div8xi16: 17 ; CHECK: mov [[TMP:(w[0-9]+)]], #40815 18 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]] 19 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h 20 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h 21 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).8h]], [[SMULL]].8h, [[SMULL2]].8h 22 ; CHECK-NEXT: add [[ADD:(v[0-9]+).8h]], [[UZP2]], v0.8h 23 ; CHECK-NEXT: sshr [[SSHR:(v[0-9]+).8h]], [[ADD]], #12 24 ; CHECK-NEXT: usra v0.8h, [[SSHR]], #15 25 %div = sdiv <8 x i16> %x, <i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577, i16 6577> 26 ret <8 x i16> %div 27 } 28 29 define <4 x i32> @div32xi4(<4 x i32> %x) { 30 ; CHECK-LABEL: div32xi4: 31 ; CHECK: mov [[TMP:(w[0-9]+)]], #7527 32 ; CHECK-NEXT: movk [[TMP]], #28805, lsl #16 33 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]] 34 ; CHECK-NEXT: smull2 [[SMULL2:(v[0-9]+)]].2d, v0.4s, [[DIVISOR]].4s 35 ; CHECK-NEXT: smull [[SMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s 36 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).4s]], [[SMULL]].4s, [[SMULL2]].4s 37 ; CHECK-NEXT: sshr [[SSHR:(v[0-9]+.4s)]], [[UZP2]], #22 38 ; CHECK-NEXT: usra v0.4s, [[UZP2]], #31 39 %div = sdiv <4 x i32> %x, <i32 9542677, i32 9542677, i32 9542677, i32 9542677> 40 ret <4 x i32> %div 41 } 42 43 define <16 x i8> @udiv16xi8(<16 x i8> %x) { 44 ; CHECK-LABEL: udiv16xi8: 45 ; CHECK: movi [[DIVISOR:(v[0-9]+)]].16b, #121 46 ; CHECK-NEXT: umull2 [[UMULL2:(v[0-9]+)]].8h, v0.16b, [[DIVISOR]].16b 47 ; CHECK-NEXT: umull [[UMULL:(v[0-9]+)]].8h, v0.8b, [[DIVISOR]].8b 48 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).16b]], [[UMULL]].16b, [[UMULL2]].16b 49 ; CHECK-NEXT: ushr v0.16b, [[UZP2]], #5 50 %div = udiv <16 x i8> %x, <i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68, i8 68> 51 ret <16 x i8> %div 52 } 53 54 define <8 x i16> @udiv8xi16(<8 x i16> %x) { 55 ; CHECK-LABEL: udiv8xi16: 56 ; CHECK: mov [[TMP:(w[0-9]+)]], #16593 57 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].8h, [[TMP]] 58 ; CHECK-NEXT: umull2 [[UMULL2:(v[0-9]+)]].4s, v0.8h, [[DIVISOR]].8h 59 ; CHECK-NEXT: umull [[UMULL:(v[0-9]+)]].4s, v0.4h, [[DIVISOR]].4h 60 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).8h]], [[UMULL]].8h, [[SMULL2]].8h 61 ; CHECK-NEXT: sub [[SUB:(v[0-9]+).8h]], v0.8h, [[UZP2]] 62 ; CHECK-NEXT: usra [[USRA:(v[0-9]+).8h]], [[SUB]], #1 63 ; CHECK-NEXT: ushr v0.8h, [[USRA]], #12 64 %div = udiv <8 x i16> %x, <i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537, i16 6537> 65 ret <8 x i16> %div 66 } 67 68 define <4 x i32> @udiv32xi4(<4 x i32> %x) { 69 ; CHECK-LABEL: udiv32xi4: 70 ; CHECK: mov [[TMP:(w[0-9]+)]], #16747 71 ; CHECK-NEXT: movk [[TMP]], #31439, lsl #16 72 ; CHECK-NEXT: dup [[DIVISOR:(v[0-9]+)]].4s, [[TMP]] 73 ; CHECK-NEXT: umull2 [[UMULL2:(v[0-9]+)]].2d, v0.4s, [[DIVISOR]].4s 74 ; CHECK-NEXT: umull [[UMULL:(v[0-9]+)]].2d, v0.2s, [[DIVISOR]].2s 75 ; CHECK-NEXT: uzp2 [[UZP2:(v[0-9]+).4s]], [[UMULL]].4s, [[SMULL2]].4s 76 ; CHECK-NEXT: ushr v0.4s, [[UZP2]], #22 77 %div = udiv <4 x i32> %x, <i32 8743143, i32 8743143, i32 8743143, i32 8743143> 78 ret <4 x i32> %div 79 } 80