1 ; RUN: llc < %s -mtriple=arm64-apple-ios3.0.0 -aarch64-neon-syntax=apple -mcpu=cyclone | FileCheck %s 2 ; ModuleID = 'arm64_vecCmpBr.c' 3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128" 4 5 6 define i32 @anyZero64(<4 x i16> %a) #0 { 7 ; CHECK: _anyZero64: 8 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0 9 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 10 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] 11 ; CHECK: [[LABEL]]: 12 ; CHECK-NEXT: b _bar 13 entry: 14 %0 = bitcast <4 x i16> %a to <8 x i8> 15 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3 16 %1 = trunc i32 %vminv.i to i8 17 %tobool = icmp eq i8 %1, 0 18 br i1 %tobool, label %if.then, label %return 19 20 if.then: ; preds = %entry 21 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4 22 br label %return 23 24 return: ; preds = %entry, %if.then 25 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ] 26 ret i32 %retval.0 27 } 28 29 declare i32 @bar(...) #1 30 31 define i32 @anyZero128(<8 x i16> %a) #0 { 32 ; CHECK: _anyZero128: 33 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0 34 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 35 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] 36 ; CHECK: [[LABEL]]: 37 ; CHECK-NEXT: b _bar 38 39 entry: 40 %0 = bitcast <8 x i16> %a to <16 x i8> 41 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3 42 %1 = trunc i32 %vminv.i to i8 43 %tobool = icmp eq i8 %1, 0 44 br i1 %tobool, label %if.then, label %return 45 46 if.then: ; preds = %entry 47 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4 48 br label %return 49 50 return: ; preds = %entry, %if.then 51 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ] 52 ret i32 %retval.0 53 } 54 55 define i32 @anyNonZero64(<4 x i16> %a) #0 { 56 ; CHECK: _anyNonZero64: 57 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0 58 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 59 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] 60 ; CHECK: [[LABEL]]: 61 ; CHECK-NEXT: mov w0, #0 62 63 entry: 64 %0 = bitcast <4 x i16> %a to <8 x i8> 65 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3 66 %1 = trunc i32 %vmaxv.i to i8 67 %tobool = icmp eq i8 %1, 0 68 br i1 %tobool, label %return, label %if.then 69 70 if.then: ; preds = %entry 71 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4 72 br label %return 73 74 return: ; preds = %entry, %if.then 75 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ] 76 ret i32 %retval.0 77 } 78 79 define i32 @anyNonZero128(<8 x i16> %a) #0 { 80 ; CHECK: _anyNonZero128: 81 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0 82 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 83 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] 84 ; CHECK: [[LABEL]]: 85 ; CHECK-NEXT: mov w0, #0 86 entry: 87 %0 = bitcast <8 x i16> %a to <16 x i8> 88 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3 89 %1 = trunc i32 %vmaxv.i to i8 90 %tobool = icmp eq i8 %1, 0 91 br i1 %tobool, label %return, label %if.then 92 93 if.then: ; preds = %entry 94 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4 95 br label %return 96 97 return: ; preds = %entry, %if.then 98 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ] 99 ret i32 %retval.0 100 } 101 102 define i32 @allZero64(<4 x i16> %a) #0 { 103 ; CHECK: _allZero64: 104 ; CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0 105 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 106 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] 107 ; CHECK: [[LABEL]]: 108 ; CHECK-NEXT: b _bar 109 entry: 110 %0 = bitcast <4 x i16> %a to <8 x i8> 111 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %0) #3 112 %1 = trunc i32 %vmaxv.i to i8 113 %tobool = icmp eq i8 %1, 0 114 br i1 %tobool, label %if.then, label %return 115 116 if.then: ; preds = %entry 117 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4 118 br label %return 119 120 return: ; preds = %entry, %if.then 121 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ] 122 ret i32 %retval.0 123 } 124 125 define i32 @allZero128(<8 x i16> %a) #0 { 126 ; CHECK: _allZero128: 127 ; CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0 128 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 129 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] 130 ; CHECK: [[LABEL]]: 131 ; CHECK-NEXT: b _bar 132 entry: 133 %0 = bitcast <8 x i16> %a to <16 x i8> 134 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3 135 %1 = trunc i32 %vmaxv.i to i8 136 %tobool = icmp eq i8 %1, 0 137 br i1 %tobool, label %if.then, label %return 138 139 if.then: ; preds = %entry 140 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4 141 br label %return 142 143 return: ; preds = %entry, %if.then 144 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ] 145 ret i32 %retval.0 146 } 147 148 define i32 @allNonZero64(<4 x i16> %a) #0 { 149 ; CHECK: _allNonZero64: 150 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0 151 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 152 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] 153 ; CHECK: [[LABEL]]: 154 ; CHECK-NEXT: mov w0, #0 155 entry: 156 %0 = bitcast <4 x i16> %a to <8 x i8> 157 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3 158 %1 = trunc i32 %vminv.i to i8 159 %tobool = icmp eq i8 %1, 0 160 br i1 %tobool, label %return, label %if.then 161 162 if.then: ; preds = %entry 163 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4 164 br label %return 165 166 return: ; preds = %entry, %if.then 167 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ] 168 ret i32 %retval.0 169 } 170 171 define i32 @allNonZero128(<8 x i16> %a) #0 { 172 ; CHECK: _allNonZero128: 173 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0 174 ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 175 ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] 176 ; CHECK: [[LABEL]]: 177 ; CHECK-NEXT: mov w0, #0 178 entry: 179 %0 = bitcast <8 x i16> %a to <16 x i8> 180 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3 181 %1 = trunc i32 %vminv.i to i8 182 %tobool = icmp eq i8 %1, 0 183 br i1 %tobool, label %return, label %if.then 184 185 if.then: ; preds = %entry 186 %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() #4 187 br label %return 188 189 return: ; preds = %entry, %if.then 190 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ] 191 ret i32 %retval.0 192 } 193 194 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) #2 195 196 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) #2 197 198 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) #2 199 200 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) #2 201 202 attributes #0 = { nounwind ssp "target-cpu"="cyclone" } 203 attributes #1 = { "target-cpu"="cyclone" } 204 attributes #2 = { nounwind readnone } 205 attributes #3 = { nounwind } 206 attributes #4 = { nobuiltin nounwind } 207
