1 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=fuse-address | FileCheck %s 2 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s 3 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s 4 5 target triple = "aarch64-unknown" 6 7 @var_8bit = global i8 0 8 @var_16bit = global i16 0 9 @var_32bit = global i32 0 10 @var_64bit = global i64 0 11 @var_128bit = global i128 0 12 @var_half = global half 0.0 13 @var_float = global float 0.0 14 @var_double = global double 0.0 15 @var_double2 = global <2 x double> <double 0.0, double 0.0> 16 17 define void @ldst_8bit() { 18 %val8 = load volatile i8, i8* @var_8bit 19 %ext = zext i8 %val8 to i64 20 %add = add i64 %ext, 1 21 %val16 = trunc i64 %add to i16 22 store volatile i16 %val16, i16* @var_16bit 23 ret void 24 25 ; CHECK-LABEL: ldst_8bit: 26 ; CHECK: adrp [[RB:x[0-9]+]], var_8bit 27 ; CHECK-NEXT: ldrb {{w[0-9]+}}, {{\[}}[[RB]], {{#?}}:lo12:var_8bit{{\]}} 28 ; CHECK: adrp [[RH:x[0-9]+]], var_16bit 29 ; CHECK-NEXT: strh {{w[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_16bit{{\]}} 30 } 31 32 define void @ldst_16bit() { 33 %val16 = load volatile i16, i16* @var_16bit 34 %ext = zext i16 %val16 to i64 35 %add = add i64 %ext, 1 36 %val32 = trunc i64 %add to i32 37 store volatile i32 %val32, i32* @var_32bit 38 ret void 39 40 ; CHECK-LABEL: ldst_16bit: 41 ; CHECK: adrp [[RH:x[0-9]+]], var_16bit 42 ; CHECK-NEXT: ldrh {{w[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_16bit{{\]}} 43 ; CHECK: adrp [[RW:x[0-9]+]], var_32bit 44 ; CHECK-NEXT: str {{w[0-9]+}}, {{\[}}[[RW]], {{#?}}:lo12:var_32bit{{\]}} 45 } 46 47 define void @ldst_32bit() { 48 %val32 = load volatile i32, i32* @var_32bit 49 %ext = zext i32 %val32 to i64 50 %val64 = add i64 %ext, 1 51 store volatile i64 %val64, i64* @var_64bit 52 ret void 53 54 ; CHECK-LABEL: ldst_32bit: 55 ; CHECK: adrp [[RW:x[0-9]+]], var_32bit 56 ; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[RW]], {{#?}}:lo12:var_32bit{{\]}} 57 ; CHECK: adrp [[RL:x[0-9]+]], var_64bit 58 ; CHECK-NEXT: str {{x[0-9]+}}, {{\[}}[[RL]], {{#?}}:lo12:var_64bit{{\]}} 59 } 60 61 define void @ldst_64bit() { 62 %val64 = load volatile i64, i64* @var_64bit 63 %ext = zext i64 %val64 to i128 64 %val128 = add i128 %ext, 1 65 store volatile i128 %val128, i128* @var_128bit 66 ret void 67 68 ; CHECK-LABEL: ldst_64bit: 69 ; CHECK: adrp [[RL:x[0-9]+]], var_64bit 70 ; CHECK-NEXT: ldr {{x[0-9]+}}, {{\[}}[[RL]], {{#?}}:lo12:var_64bit{{\]}} 71 ; CHECK: adrp [[RQ:x[0-9]+]], var_128bit 72 ; CHECK-NEXT: add {{x[0-9]+}}, [[RQ]], {{#?}}:lo12:var_128bit 73 } 74 75 define void @ldst_half() { 76 %valh = load volatile half, half* @var_half 77 %valf = fpext half %valh to float 78 store volatile float %valf, float* @var_float 79 ret void 80 81 ; CHECK-LABEL: ldst_half: 82 ; CHECK: adrp [[RH:x[0-9]+]], var_half 83 ; CHECK-NEXT: ldr {{h[0-9]+}}, {{\[}}[[RH]], {{#?}}:lo12:var_half{{\]}} 84 ; CHECK: adrp [[RF:x[0-9]+]], var_float 85 ; CHECK-NEXT: str {{s[0-9]+}}, {{\[}}[[RF]], {{#?}}:lo12:var_float{{\]}} 86 } 87 88 define void @ldst_float() { 89 %valf = load volatile float, float* @var_float 90 %vald = fpext float %valf to double 91 store volatile double %vald, double* @var_double 92 ret void 93 94 ; CHECK-LABEL: ldst_float: 95 ; CHECK: adrp [[RF:x[0-9]+]], var_float 96 ; CHECK-NEXT: ldr {{s[0-9]+}}, {{\[}}[[RF]], {{#?}}:lo12:var_float{{\]}} 97 ; CHECK: adrp [[RD:x[0-9]+]], var_double 98 ; CHECK-NEXT: str {{d[0-9]+}}, {{\[}}[[RD]], {{#?}}:lo12:var_double{{\]}} 99 } 100 101 define void @ldst_double() { 102 %valf = load volatile float, float* @var_float 103 %vale = fpext float %valf to double 104 %vald = load volatile double, double* @var_double 105 %vald1 = insertelement <2 x double> undef, double %vald, i32 0 106 %vald2 = insertelement <2 x double> %vald1, double %vale, i32 1 107 store volatile <2 x double> %vald2, <2 x double>* @var_double2 108 ret void 109 110 ; CHECK-LABEL: ldst_double: 111 ; CHECK: adrp [[RD:x[0-9]+]], var_double 112 ; CHECK-NEXT: ldr {{d[0-9]+}}, {{\[}}[[RD]], {{#?}}:lo12:var_double{{\]}} 113 ; CHECK: adrp [[RQ:x[0-9]+]], var_double2 114 ; CHECK-NEXT: str {{q[0-9]+}}, {{\[}}[[RQ]], {{#?}}:lo12:var_double2{{\]}} 115 } 116
