1 ; REQUIRES: asserts 2 ; RUN: llc < %s -mtriple=aarch64 -mcpu=cyclone -mattr=+use-aa,+slow-misaligned-128store -enable-misched -verify-misched -o - | FileCheck %s 3 4 ; Tests to check that the scheduler dependencies derived from alias analysis are 5 ; correct when we have loads that have been split up so that they can later be 6 ; merged into STP. 7 8 ; Now that overwritten stores are elided in SelectionDAG, dependencies 9 ; are resolved and removed before MISCHED. Check that we have 10 ; equivalent pair of stp calls as a baseline. 11 12 ; CHECK-LABEL: test_splat 13 ; CHECK: ldr [[REG:w[0-9]+]], [x2] 14 ; CHECK-DAG: stp w0, [[REG]], [x2, #12] 15 ; CHECK-DAG: stp [[REG]], w1, [x2, #4] 16 define void @test_splat(i32 %x, i32 %y, i32* %p) { 17 entry: 18 %val = load i32, i32* %p, align 4 19 %0 = getelementptr inbounds i32, i32* %p, i64 1 20 %1 = getelementptr inbounds i32, i32* %p, i64 2 21 %2 = getelementptr inbounds i32, i32* %p, i64 3 22 %vec0 = insertelement <4 x i32> undef, i32 %val, i32 0 23 %vec1 = insertelement <4 x i32> %vec0, i32 %val, i32 1 24 %vec2 = insertelement <4 x i32> %vec1, i32 %val, i32 2 25 %vec3 = insertelement <4 x i32> %vec2, i32 %val, i32 3 26 %3 = bitcast i32* %0 to <4 x i32>* 27 store <4 x i32> %vec3, <4 x i32>* %3, align 4 28 store i32 %x, i32* %2, align 4 29 store i32 %y, i32* %1, align 4 30 ret void 31 } 32 33 declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) 34 %struct.tree_common = type { i8*, i8*, i32 } 35 36 ; CHECK-LABEL: test_zero 37 ; CHECK-DAG: stp x2, xzr, [x0, #8] 38 ; CHECK-DAG: str w1, [x0, #16] 39 ; CHECK-DAG: str xzr, [x0] 40 41 define void @test_zero(%struct.tree_common* %t, i32 %code, i8* %type) { 42 entry: 43 %0 = bitcast %struct.tree_common* %t to i8* 44 tail call void @llvm.memset.p0i8.i64(i8* align 8 %0, i8 0, i64 24, i1 false) 45 %code1 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 2 46 store i32 %code, i32* %code1, align 8 47 %type2 = getelementptr inbounds %struct.tree_common, %struct.tree_common* %t, i64 0, i32 1 48 store i8* %type, i8** %type2, align 8 49 ret void 50 } 51
