1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s 2 3 define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) { 4 ; CHECK-LABEL: and8xi8: 5 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 6 %tmp1 = and <8 x i8> %a, %b; 7 ret <8 x i8> %tmp1 8 } 9 10 define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) { 11 ; CHECK-LABEL: and16xi8: 12 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 13 %tmp1 = and <16 x i8> %a, %b; 14 ret <16 x i8> %tmp1 15 } 16 17 18 define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) { 19 ; CHECK-LABEL: orr8xi8: 20 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 21 %tmp1 = or <8 x i8> %a, %b; 22 ret <8 x i8> %tmp1 23 } 24 25 define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) { 26 ; CHECK-LABEL: orr16xi8: 27 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 28 %tmp1 = or <16 x i8> %a, %b; 29 ret <16 x i8> %tmp1 30 } 31 32 33 define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) { 34 ; CHECK-LABEL: xor8xi8: 35 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 36 %tmp1 = xor <8 x i8> %a, %b; 37 ret <8 x i8> %tmp1 38 } 39 40 define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) { 41 ; CHECK-LABEL: xor16xi8: 42 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 43 %tmp1 = xor <16 x i8> %a, %b; 44 ret <16 x i8> %tmp1 45 } 46 47 define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) { 48 ; CHECK-LABEL: bsl8xi8_const: 49 ; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff0000ffff 50 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 51 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0 > 52 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 -1, i8 -1 > 53 %tmp3 = or <8 x i8> %tmp1, %tmp2 54 ret <8 x i8> %tmp3 55 } 56 57 define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) { 58 ; CHECK-LABEL: bsl16xi8_const: 59 ; CHECK: movi {{v[0-9]+}}.2d, #0x{{0*}}ffffffff 60 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 61 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0 > 62 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 -1 > 63 %tmp3 = or <16 x i8> %tmp1, %tmp2 64 ret <16 x i8> %tmp3 65 } 66 67 define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) { 68 ; CHECK-LABEL: orn8xi8: 69 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 70 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > 71 %tmp2 = or <8 x i8> %a, %tmp1 72 ret <8 x i8> %tmp2 73 } 74 75 define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) { 76 ; CHECK-LABEL: orn16xi8: 77 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 78 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > 79 %tmp2 = or <16 x i8> %a, %tmp1 80 ret <16 x i8> %tmp2 81 } 82 83 define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) { 84 ; CHECK-LABEL: bic8xi8: 85 ; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 86 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > 87 %tmp2 = and <8 x i8> %a, %tmp1 88 ret <8 x i8> %tmp2 89 } 90 91 define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) { 92 ; CHECK-LABEL: bic16xi8: 93 ; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 94 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > 95 %tmp2 = and <16 x i8> %a, %tmp1 96 ret <16 x i8> %tmp2 97 } 98 99 define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) { 100 ; CHECK-LABEL: orrimm2s_lsl0: 101 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}} 102 %tmp1 = or <2 x i32> %a, < i32 255, i32 255> 103 ret <2 x i32> %tmp1 104 } 105 106 define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) { 107 ; CHECK-LABEL: orrimm2s_lsl8: 108 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 109 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280> 110 ret <2 x i32> %tmp1 111 } 112 113 define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) { 114 ; CHECK-LABEL: orrimm2s_lsl16: 115 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 116 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680> 117 ret <2 x i32> %tmp1 118 } 119 120 define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) { 121 ; CHECK-LABEL: orrimm2s_lsl24: 122 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24 123 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080> 124 ret <2 x i32> %tmp1 125 } 126 127 define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) { 128 ; CHECK-LABEL: orrimm4s_lsl0: 129 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}} 130 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255> 131 ret <4 x i32> %tmp1 132 } 133 134 define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) { 135 ; CHECK-LABEL: orrimm4s_lsl8: 136 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 137 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280> 138 ret <4 x i32> %tmp1 139 } 140 141 define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) { 142 ; CHECK-LABEL: orrimm4s_lsl16: 143 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 144 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680> 145 ret <4 x i32> %tmp1 146 } 147 148 define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) { 149 ; CHECK-LABEL: orrimm4s_lsl24: 150 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24 151 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080> 152 ret <4 x i32> %tmp1 153 } 154 155 define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) { 156 ; CHECK-LABEL: orrimm4h_lsl0: 157 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}} 158 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 > 159 ret <4 x i16> %tmp1 160 } 161 162 define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) { 163 ; CHECK-LABEL: orrimm4h_lsl8: 164 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 165 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 > 166 ret <4 x i16> %tmp1 167 } 168 169 define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) { 170 ; CHECK-LABEL: orrimm8h_lsl0: 171 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}} 172 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 > 173 ret <8 x i16> %tmp1 174 } 175 176 define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) { 177 ; CHECK-LABEL: orrimm8h_lsl8: 178 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 179 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 > 180 ret <8 x i16> %tmp1 181 } 182 183 define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) { 184 ; CHECK-LABEL: bicimm2s_lsl0: 185 ; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}} 186 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 > 187 ret <2 x i32> %tmp1 188 } 189 190 define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) { 191 ; CHECK-LABEL: bicimm2s_lsl8: 192 ; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #8 193 %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 > 194 ret <2 x i32> %tmp1 195 } 196 197 define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) { 198 ; CHECK-LABEL: bicimm2s_lsl16: 199 ; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #16 200 %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 > 201 ret <2 x i32> %tmp1 202 } 203 204 define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) { 205 ; CHECK-LABEL: bicimm2s_lsl124: 206 ; CHECK: bic {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #24 207 %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839> 208 ret <2 x i32> %tmp1 209 } 210 211 define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) { 212 ; CHECK-LABEL: bicimm4s_lsl0: 213 ; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}} 214 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 > 215 ret <4 x i32> %tmp1 216 } 217 218 define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) { 219 ; CHECK-LABEL: bicimm4s_lsl8: 220 ; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #8 221 %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 > 222 ret <4 x i32> %tmp1 223 } 224 225 define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) { 226 ; CHECK-LABEL: bicimm4s_lsl16: 227 ; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #16 228 %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 > 229 ret <4 x i32> %tmp1 230 } 231 232 define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) { 233 ; CHECK-LABEL: bicimm4s_lsl124: 234 ; CHECK: bic {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #24 235 %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839> 236 ret <4 x i32> %tmp1 237 } 238 239 define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) { 240 ; CHECK-LABEL: bicimm4h_lsl0_a: 241 ; CHECK: bic {{v[0-9]+}}.4h, #{{0x10|16}} 242 %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 > 243 ret <4 x i16> %tmp1 244 } 245 246 define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) { 247 ; CHECK-LABEL: bicimm4h_lsl0_b: 248 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}} 249 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 > 250 ret <4 x i16> %tmp1 251 } 252 253 define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) { 254 ; CHECK-LABEL: bicimm4h_lsl8_a: 255 ; CHECK: bic {{v[0-9]+}}.4h, #{{0x10|16}}, lsl #8 256 %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199> 257 ret <4 x i16> %tmp1 258 } 259 260 define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) { 261 ; CHECK-LABEL: bicimm4h_lsl8_b: 262 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 263 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255> 264 ret <4 x i16> %tmp1 265 } 266 267 define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) { 268 ; CHECK-LABEL: bicimm8h_lsl0_a: 269 ; CHECK: bic {{v[0-9]+}}.8h, #{{0x10|16}} 270 %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279, 271 i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 > 272 ret <8 x i16> %tmp1 273 } 274 275 define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) { 276 ; CHECK-LABEL: bicimm8h_lsl0_b: 277 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}} 278 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 > 279 ret <8 x i16> %tmp1 280 } 281 282 define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) { 283 ; CHECK-LABEL: bicimm8h_lsl8_a: 284 ; CHECK: bic {{v[0-9]+}}.8h, #{{0x10|16}}, lsl #8 285 %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199, 286 i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199> 287 ret <8 x i16> %tmp1 288 } 289 290 define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) { 291 ; CHECK-LABEL: bicimm8h_lsl8_b: 292 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 293 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> 294 ret <8 x i16> %tmp1 295 } 296 297 define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) { 298 ; CHECK-LABEL: and2xi32: 299 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 300 %tmp1 = and <2 x i32> %a, %b; 301 ret <2 x i32> %tmp1 302 } 303 304 define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) { 305 ; CHECK-LABEL: and4xi16: 306 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 307 %tmp1 = and <4 x i16> %a, %b; 308 ret <4 x i16> %tmp1 309 } 310 311 define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) { 312 ; CHECK-LABEL: and1xi64: 313 ; CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 314 %tmp1 = and <1 x i64> %a, %b; 315 ret <1 x i64> %tmp1 316 } 317 318 define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) { 319 ; CHECK-LABEL: and4xi32: 320 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 321 %tmp1 = and <4 x i32> %a, %b; 322 ret <4 x i32> %tmp1 323 } 324 325 define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) { 326 ; CHECK-LABEL: and8xi16: 327 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 328 %tmp1 = and <8 x i16> %a, %b; 329 ret <8 x i16> %tmp1 330 } 331 332 define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) { 333 ; CHECK-LABEL: and2xi64: 334 ; CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 335 %tmp1 = and <2 x i64> %a, %b; 336 ret <2 x i64> %tmp1 337 } 338 339 define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) { 340 ; CHECK-LABEL: orr2xi32: 341 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 342 %tmp1 = or <2 x i32> %a, %b; 343 ret <2 x i32> %tmp1 344 } 345 346 define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) { 347 ; CHECK-LABEL: orr4xi16: 348 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 349 %tmp1 = or <4 x i16> %a, %b; 350 ret <4 x i16> %tmp1 351 } 352 353 define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) { 354 ; CHECK-LABEL: orr1xi64: 355 ; CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 356 %tmp1 = or <1 x i64> %a, %b; 357 ret <1 x i64> %tmp1 358 } 359 360 define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) { 361 ; CHECK-LABEL: orr4xi32: 362 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 363 %tmp1 = or <4 x i32> %a, %b; 364 ret <4 x i32> %tmp1 365 } 366 367 define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) { 368 ; CHECK-LABEL: orr8xi16: 369 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 370 %tmp1 = or <8 x i16> %a, %b; 371 ret <8 x i16> %tmp1 372 } 373 374 define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) { 375 ; CHECK-LABEL: orr2xi64: 376 ; CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 377 %tmp1 = or <2 x i64> %a, %b; 378 ret <2 x i64> %tmp1 379 } 380 381 define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) { 382 ; CHECK-LABEL: eor2xi32: 383 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 384 %tmp1 = xor <2 x i32> %a, %b; 385 ret <2 x i32> %tmp1 386 } 387 388 define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) { 389 ; CHECK-LABEL: eor4xi16: 390 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 391 %tmp1 = xor <4 x i16> %a, %b; 392 ret <4 x i16> %tmp1 393 } 394 395 define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) { 396 ; CHECK-LABEL: eor1xi64: 397 ; CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 398 %tmp1 = xor <1 x i64> %a, %b; 399 ret <1 x i64> %tmp1 400 } 401 402 define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) { 403 ; CHECK-LABEL: eor4xi32: 404 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 405 %tmp1 = xor <4 x i32> %a, %b; 406 ret <4 x i32> %tmp1 407 } 408 409 define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) { 410 ; CHECK-LABEL: eor8xi16: 411 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 412 %tmp1 = xor <8 x i16> %a, %b; 413 ret <8 x i16> %tmp1 414 } 415 416 define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) { 417 ; CHECK-LABEL: eor2xi64: 418 ; CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 419 %tmp1 = xor <2 x i64> %a, %b; 420 ret <2 x i64> %tmp1 421 } 422 423 424 define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) { 425 ; CHECK-LABEL: bic2xi32: 426 ; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 427 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 > 428 %tmp2 = and <2 x i32> %a, %tmp1 429 ret <2 x i32> %tmp2 430 } 431 432 define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) { 433 ; CHECK-LABEL: bic4xi16: 434 ; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 435 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 > 436 %tmp2 = and <4 x i16> %a, %tmp1 437 ret <4 x i16> %tmp2 438 } 439 440 define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) { 441 ; CHECK-LABEL: bic1xi64: 442 ; CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 443 %tmp1 = xor <1 x i64> %b, < i64 -1> 444 %tmp2 = and <1 x i64> %a, %tmp1 445 ret <1 x i64> %tmp2 446 } 447 448 define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) { 449 ; CHECK-LABEL: bic4xi32: 450 ; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 451 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1> 452 %tmp2 = and <4 x i32> %a, %tmp1 453 ret <4 x i32> %tmp2 454 } 455 456 define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) { 457 ; CHECK-LABEL: bic8xi16: 458 ; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 459 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 > 460 %tmp2 = and <8 x i16> %a, %tmp1 461 ret <8 x i16> %tmp2 462 } 463 464 define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) { 465 ; CHECK-LABEL: bic2xi64: 466 ; CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 467 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1> 468 %tmp2 = and <2 x i64> %a, %tmp1 469 ret <2 x i64> %tmp2 470 } 471 472 define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) { 473 ; CHECK-LABEL: orn2xi32: 474 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 475 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 > 476 %tmp2 = or <2 x i32> %a, %tmp1 477 ret <2 x i32> %tmp2 478 } 479 480 define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) { 481 ; CHECK-LABEL: orn4xi16: 482 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 483 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 > 484 %tmp2 = or <4 x i16> %a, %tmp1 485 ret <4 x i16> %tmp2 486 } 487 488 define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) { 489 ; CHECK-LABEL: orn1xi64: 490 ; CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 491 %tmp1 = xor <1 x i64> %b, < i64 -1> 492 %tmp2 = or <1 x i64> %a, %tmp1 493 ret <1 x i64> %tmp2 494 } 495 496 define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) { 497 ; CHECK-LABEL: orn4xi32: 498 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 499 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1> 500 %tmp2 = or <4 x i32> %a, %tmp1 501 ret <4 x i32> %tmp2 502 } 503 504 define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) { 505 ; CHECK-LABEL: orn8xi16: 506 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 507 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 > 508 %tmp2 = or <8 x i16> %a, %tmp1 509 ret <8 x i16> %tmp2 510 } 511 512 define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) { 513 ; CHECK-LABEL: orn2xi64: 514 ; CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 515 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1> 516 %tmp2 = or <2 x i64> %a, %tmp1 517 ret <2 x i64> %tmp2 518 } 519 520 define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) { 521 ; CHECK-LABEL: bsl2xi32_const: 522 ; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffffffff 523 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 524 %tmp1 = and <2 x i32> %a, < i32 -1, i32 0 > 525 %tmp2 = and <2 x i32> %b, < i32 0, i32 -1 > 526 %tmp3 = or <2 x i32> %tmp1, %tmp2 527 ret <2 x i32> %tmp3 528 } 529 530 531 define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) { 532 ; CHECK-LABEL: bsl4xi16_const: 533 ; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff0000ffff 534 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 535 %tmp1 = and <4 x i16> %a, < i16 -1, i16 0, i16 -1,i16 0 > 536 %tmp2 = and <4 x i16> %b, < i16 0, i16 -1,i16 0, i16 -1 > 537 %tmp3 = or <4 x i16> %tmp1, %tmp2 538 ret <4 x i16> %tmp3 539 } 540 541 define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) { 542 ; CHECK-LABEL: bsl1xi64_const: 543 ; CHECK: movi {{d[0-9]+}}, #0xffffffffffffff00 544 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 545 %tmp1 = and <1 x i64> %a, < i64 -256 > 546 %tmp2 = and <1 x i64> %b, < i64 255 > 547 %tmp3 = or <1 x i64> %tmp1, %tmp2 548 ret <1 x i64> %tmp3 549 } 550 551 define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) { 552 ; CHECK-LABEL: bsl4xi32_const: 553 ; CHECK: movi {{v[0-9]+}}.2d, #0x{{0*}}ffffffff 554 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 555 %tmp1 = and <4 x i32> %a, < i32 -1, i32 0, i32 -1, i32 0 > 556 %tmp2 = and <4 x i32> %b, < i32 0, i32 -1, i32 0, i32 -1 > 557 %tmp3 = or <4 x i32> %tmp1, %tmp2 558 ret <4 x i32> %tmp3 559 } 560 561 define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) { 562 ; CHECK-LABEL: bsl8xi16_const: 563 ; CHECK: movi {{v[0-9]+}}.2d, #0x{{0*}}ffffffff 564 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 565 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 0,i16 0, i16 -1, i16 -1, i16 0,i16 0 > 566 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 -1, i16 -1 > 567 %tmp3 = or <8 x i16> %tmp1, %tmp2 568 ret <8 x i16> %tmp3 569 } 570 571 define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) { 572 ; CHECK-LABEL: bsl2xi64_const: 573 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 574 %tmp1 = and <2 x i64> %a, < i64 -1, i64 0 > 575 %tmp2 = and <2 x i64> %b, < i64 0, i64 -1 > 576 %tmp3 = or <2 x i64> %tmp1, %tmp2 577 ret <2 x i64> %tmp3 578 } 579 580 581 define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) { 582 ; CHECK-LABEL: bsl8xi8: 583 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 584 %1 = and <8 x i8> %v1, %v2 585 %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 586 %3 = and <8 x i8> %2, %v3 587 %4 = or <8 x i8> %1, %3 588 ret <8 x i8> %4 589 } 590 591 define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) { 592 ; CHECK-LABEL: bsl4xi16: 593 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 594 %1 = and <4 x i16> %v1, %v2 595 %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1> 596 %3 = and <4 x i16> %2, %v3 597 %4 = or <4 x i16> %1, %3 598 ret <4 x i16> %4 599 } 600 601 define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) { 602 ; CHECK-LABEL: bsl2xi32: 603 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 604 %1 = and <2 x i32> %v1, %v2 605 %2 = xor <2 x i32> %v1, <i32 -1, i32 -1> 606 %3 = and <2 x i32> %2, %v3 607 %4 = or <2 x i32> %1, %3 608 ret <2 x i32> %4 609 } 610 611 define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) { 612 ; CHECK-LABEL: bsl1xi64: 613 ; CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 614 %1 = and <1 x i64> %v1, %v2 615 %2 = xor <1 x i64> %v1, <i64 -1> 616 %3 = and <1 x i64> %2, %v3 617 %4 = or <1 x i64> %1, %3 618 ret <1 x i64> %4 619 } 620 621 define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) { 622 ; CHECK-LABEL: bsl16xi8: 623 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 624 %1 = and <16 x i8> %v1, %v2 625 %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 626 %3 = and <16 x i8> %2, %v3 627 %4 = or <16 x i8> %1, %3 628 ret <16 x i8> %4 629 } 630 631 define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) { 632 ; CHECK-LABEL: bsl8xi16: 633 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 634 %1 = and <8 x i16> %v1, %v2 635 %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 636 %3 = and <8 x i16> %2, %v3 637 %4 = or <8 x i16> %1, %3 638 ret <8 x i16> %4 639 } 640 641 define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) { 642 ; CHECK-LABEL: bsl4xi32: 643 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 644 %1 = and <4 x i32> %v1, %v2 645 %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1> 646 %3 = and <4 x i32> %2, %v3 647 %4 = or <4 x i32> %1, %3 648 ret <4 x i32> %4 649 } 650 651 define <8 x i8> @vselect_v8i8(<8 x i8> %a) { 652 ; CHECK-LABEL: vselect_v8i8: 653 ; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff 654 ; CHECK-NEXT: {{bsl v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b|and v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b}} 655 %b = select <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> <i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> 656 ret <8 x i8> %b 657 } 658 659 define <4 x i16> @vselect_v4i16(<4 x i16> %a) { 660 ; CHECK-LABEL: vselect_v4i16: 661 ; CHECK: movi {{d[0-9]+}}, #0x{{0*}}ffff 662 ; CHECK-NEXT: {{bsl v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b|and v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b}} 663 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> %a, <4 x i16> <i16 undef, i16 0, i16 0, i16 0> 664 ret <4 x i16> %b 665 } 666 667 define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 668 ; CHECK-LABEL: vselect_cmp_ne: 669 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 670 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 671 ; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 672 %cmp = icmp ne <8 x i8> %a, %b 673 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c 674 ret <8 x i8> %d 675 } 676 677 define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 678 ; CHECK-LABEL: vselect_cmp_eq: 679 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 680 ; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 681 %cmp = icmp eq <8 x i8> %a, %b 682 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c 683 ret <8 x i8> %d 684 } 685 686 define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 687 ; CHECK-LABEL: vselect_cmpz_ne: 688 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0 689 ; CHECK-NEXT: {{mvn|not}} {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 690 ; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 691 %cmp = icmp ne <8 x i8> %a, zeroinitializer 692 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c 693 ret <8 x i8> %d 694 } 695 696 define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 697 ; CHECK-LABEL: vselect_cmpz_eq: 698 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0 699 ; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 700 %cmp = icmp eq <8 x i8> %a, zeroinitializer 701 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c 702 ret <8 x i8> %d 703 } 704 705 define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) { 706 ; CHECK-LABEL: vselect_tst: 707 ; CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 708 ; CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 709 %tmp3 = and <8 x i8> %a, %b 710 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer 711 %d = select <8 x i1> %tmp4, <8 x i8> %b, <8 x i8> %c 712 ret <8 x i8> %d 713 } 714 715 define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) { 716 ; CHECK-LABEL: bsl2xi64: 717 ; CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 718 %1 = and <2 x i64> %v1, %v2 719 %2 = xor <2 x i64> %v1, <i64 -1, i64 -1> 720 %3 = and <2 x i64> %2, %v3 721 %4 = or <2 x i64> %1, %3 722 ret <2 x i64> %4 723 } 724 725 define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) { 726 ; CHECK-LABEL: orrimm8b_as_orrimm4h_lsl0: 727 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}} 728 %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> 729 ret <8 x i8> %val 730 } 731 732 define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) { 733 ; CHECK-LABEL: orrimm8b_as_orimm4h_lsl8: 734 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 735 %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 736 ret <8 x i8> %val 737 } 738 739 define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) { 740 ; CHECK-LABEL: orimm16b_as_orrimm8h_lsl0: 741 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}} 742 %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> 743 ret <16 x i8> %val 744 } 745 746 define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) { 747 ; CHECK-LABEL: orimm16b_as_orrimm8h_lsl8: 748 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 749 %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 750 ret <16 x i8> %val 751 } 752 753 define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) { 754 ; CHECK-LABEL: and8imm2s_lsl0: 755 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}} 756 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255> 757 ret <8 x i8> %tmp1 758 } 759 760 define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) { 761 ; CHECK-LABEL: and8imm2s_lsl8: 762 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 763 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255> 764 ret <8 x i8> %tmp1 765 } 766 767 define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) { 768 ; CHECK-LABEL: and8imm2s_lsl16: 769 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 770 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255> 771 ret <8 x i8> %tmp1 772 } 773 774 define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) { 775 ; CHECK-LABEL: and8imm2s_lsl24: 776 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24 777 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1> 778 ret <8 x i8> %tmp1 779 } 780 781 define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) { 782 ; CHECK-LABEL: and16imm2s_lsl0: 783 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}} 784 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535> 785 ret <4 x i16> %tmp1 786 } 787 788 define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) { 789 ; CHECK-LABEL: and16imm2s_lsl8: 790 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 791 %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535> 792 ret <4 x i16> %tmp1 793 } 794 795 define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) { 796 ; CHECK-LABEL: and16imm2s_lsl16: 797 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 798 %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280> 799 ret <4 x i16> %tmp1 800 } 801 802 define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) { 803 ; CHECK-LABEL: and16imm2s_lsl24: 804 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24 805 %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511> 806 ret <4 x i16> %tmp1 807 } 808 809 810 define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) { 811 ; CHECK-LABEL: and64imm2s_lsl0: 812 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}} 813 %tmp1 = and <1 x i64> %a, < i64 -1095216660736> 814 ret <1 x i64> %tmp1 815 } 816 817 define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) { 818 ; CHECK-LABEL: and64imm2s_lsl8: 819 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 820 %tmp1 = and <1 x i64> %a, < i64 -280375465148161> 821 ret <1 x i64> %tmp1 822 } 823 824 define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) { 825 ; CHECK-LABEL: and64imm2s_lsl16: 826 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 827 %tmp1 = and <1 x i64> %a, < i64 -71776119077928961> 828 ret <1 x i64> %tmp1 829 } 830 831 define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) { 832 ; CHECK-LABEL: and64imm2s_lsl24: 833 ; CHECK: bic {{v[0-9]+}}.2s, #{{0xfe|254}}, lsl #24 834 %tmp1 = and <1 x i64> %a, < i64 144115183814443007> 835 ret <1 x i64> %tmp1 836 } 837 838 define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) { 839 ; CHECK-LABEL: and8imm4s_lsl0: 840 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}} 841 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255> 842 ret <16 x i8> %tmp1 843 } 844 845 define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) { 846 ; CHECK-LABEL: and8imm4s_lsl8: 847 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 848 %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255> 849 ret <16 x i8> %tmp1 850 } 851 852 define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) { 853 ; CHECK-LABEL: and8imm4s_lsl16: 854 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 855 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255> 856 ret <16 x i8> %tmp1 857 } 858 859 define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) { 860 ; CHECK-LABEL: and8imm4s_lsl24: 861 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24 862 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1> 863 ret <16 x i8> %tmp1 864 } 865 866 define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) { 867 ; CHECK-LABEL: and16imm4s_lsl0: 868 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}} 869 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535> 870 ret <8 x i16> %tmp1 871 } 872 873 define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) { 874 ; CHECK-LABEL: and16imm4s_lsl8: 875 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 876 %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535> 877 ret <8 x i16> %tmp1 878 } 879 880 define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) { 881 ; CHECK-LABEL: and16imm4s_lsl16: 882 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 883 %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280> 884 ret <8 x i16> %tmp1 885 } 886 887 define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) { 888 ; CHECK-LABEL: and16imm4s_lsl24: 889 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24 890 %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511> 891 ret <8 x i16> %tmp1 892 } 893 894 define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) { 895 ; CHECK-LABEL: and64imm4s_lsl0: 896 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}} 897 %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736> 898 ret <2 x i64> %tmp1 899 } 900 901 define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) { 902 ; CHECK-LABEL: and64imm4s_lsl8: 903 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 904 %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161> 905 ret <2 x i64> %tmp1 906 } 907 908 define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) { 909 ; CHECK-LABEL: and64imm4s_lsl16: 910 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 911 %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961> 912 ret <2 x i64> %tmp1 913 } 914 915 define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) { 916 ; CHECK-LABEL: and64imm4s_lsl24: 917 ; CHECK: bic {{v[0-9]+}}.4s, #{{0xfe|254}}, lsl #24 918 %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007> 919 ret <2 x i64> %tmp1 920 } 921 922 define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) { 923 ; CHECK-LABEL: and8imm4h_lsl0: 924 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}} 925 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 926 ret <8 x i8> %tmp1 927 } 928 929 define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) { 930 ; CHECK-LABEL: and8imm4h_lsl8: 931 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 932 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> 933 ret <8 x i8> %tmp1 934 } 935 936 define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) { 937 ; CHECK-LABEL: and16imm4h_lsl0: 938 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}} 939 %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360> 940 ret <2 x i32> %tmp1 941 } 942 943 define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) { 944 ; CHECK-LABEL: and16imm4h_lsl8: 945 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 946 %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935> 947 ret <2 x i32> %tmp1 948 } 949 950 define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) { 951 ; CHECK-LABEL: and64imm4h_lsl0: 952 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}} 953 %tmp1 = and <1 x i64> %a, < i64 -71777214294589696> 954 ret <1 x i64> %tmp1 955 } 956 957 define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) { 958 ; CHECK-LABEL: and64imm4h_lsl8: 959 ; CHECK: bic {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 960 %tmp1 = and <1 x i64> %a, < i64 71777214294589695> 961 ret <1 x i64> %tmp1 962 } 963 964 define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) { 965 ; CHECK-LABEL: and8imm8h_lsl0: 966 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}} 967 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 > 968 ret <16 x i8> %tmp1 969 } 970 971 define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) { 972 ; CHECK-LABEL: and8imm8h_lsl8: 973 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 974 %tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 > 975 ret <16 x i8> %tmp1 976 } 977 978 define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) { 979 ; CHECK-LABEL: and16imm8h_lsl0: 980 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}} 981 %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360> 982 ret <4 x i32> %tmp1 983 } 984 985 define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) { 986 ; CHECK-LABEL: and16imm8h_lsl8: 987 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 988 %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935> 989 ret <4 x i32> %tmp1 990 } 991 992 define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) { 993 ; CHECK-LABEL: and64imm8h_lsl0: 994 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}} 995 %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696> 996 ret <2 x i64> %tmp1 997 } 998 999 define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) { 1000 ; CHECK-LABEL: and64imm8h_lsl8: 1001 ; CHECK: bic {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 1002 %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695> 1003 ret <2 x i64> %tmp1 1004 } 1005 1006 define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) { 1007 ; CHECK-LABEL: orr8imm2s_lsl0: 1008 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}} 1009 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0> 1010 ret <8 x i8> %tmp1 1011 } 1012 1013 define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) { 1014 ; CHECK-LABEL: orr8imm2s_lsl8: 1015 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 1016 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0> 1017 ret <8 x i8> %tmp1 1018 } 1019 1020 define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) { 1021 ; CHECK-LABEL: orr8imm2s_lsl16: 1022 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 1023 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0> 1024 ret <8 x i8> %tmp1 1025 } 1026 1027 define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) { 1028 ; CHECK-LABEL: orr8imm2s_lsl24: 1029 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24 1030 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255> 1031 ret <8 x i8> %tmp1 1032 } 1033 1034 define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) { 1035 ; CHECK-LABEL: orr16imm2s_lsl0: 1036 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}} 1037 %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0> 1038 ret <4 x i16> %tmp1 1039 } 1040 1041 define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) { 1042 ; CHECK-LABEL: orr16imm2s_lsl8: 1043 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 1044 %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0> 1045 ret <4 x i16> %tmp1 1046 } 1047 1048 define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) { 1049 ; CHECK-LABEL: orr16imm2s_lsl16: 1050 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 1051 %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255> 1052 ret <4 x i16> %tmp1 1053 } 1054 1055 define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) { 1056 ; CHECK-LABEL: orr16imm2s_lsl24: 1057 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24 1058 %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280> 1059 ret <4 x i16> %tmp1 1060 } 1061 1062 define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) { 1063 ; CHECK-LABEL: orr64imm2s_lsl0: 1064 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}} 1065 %tmp1 = or <1 x i64> %a, < i64 1095216660735> 1066 ret <1 x i64> %tmp1 1067 } 1068 1069 define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) { 1070 ; CHECK-LABEL: orr64imm2s_lsl8: 1071 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #8 1072 %tmp1 = or <1 x i64> %a, < i64 280375465148160> 1073 ret <1 x i64> %tmp1 1074 } 1075 1076 define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) { 1077 ; CHECK-LABEL: orr64imm2s_lsl16: 1078 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #16 1079 %tmp1 = or <1 x i64> %a, < i64 71776119077928960> 1080 ret <1 x i64> %tmp1 1081 } 1082 1083 define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) { 1084 ; CHECK-LABEL: orr64imm2s_lsl24: 1085 ; CHECK: orr {{v[0-9]+}}.2s, #{{0xff|255}}, lsl #24 1086 %tmp1 = or <1 x i64> %a, < i64 -72057589759737856> 1087 ret <1 x i64> %tmp1 1088 } 1089 1090 define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) { 1091 ; CHECK-LABEL: orr8imm4s_lsl0: 1092 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}} 1093 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0> 1094 ret <16 x i8> %tmp1 1095 } 1096 1097 define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) { 1098 ; CHECK-LABEL: orr8imm4s_lsl8: 1099 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 1100 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0> 1101 ret <16 x i8> %tmp1 1102 } 1103 1104 define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) { 1105 ; CHECK-LABEL: orr8imm4s_lsl16: 1106 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 1107 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0> 1108 ret <16 x i8> %tmp1 1109 } 1110 1111 define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) { 1112 ; CHECK-LABEL: orr8imm4s_lsl24: 1113 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24 1114 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255> 1115 ret <16 x i8> %tmp1 1116 } 1117 1118 define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) { 1119 ; CHECK-LABEL: orr16imm4s_lsl0: 1120 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}} 1121 %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0> 1122 ret <8 x i16> %tmp1 1123 } 1124 1125 define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) { 1126 ; CHECK-LABEL: orr16imm4s_lsl8: 1127 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 1128 %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0> 1129 ret <8 x i16> %tmp1 1130 } 1131 1132 define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) { 1133 ; CHECK-LABEL: orr16imm4s_lsl16: 1134 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 1135 %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255> 1136 ret <8 x i16> %tmp1 1137 } 1138 1139 define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) { 1140 ; CHECK-LABEL: orr16imm4s_lsl24: 1141 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24 1142 %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280> 1143 ret <8 x i16> %tmp1 1144 } 1145 1146 define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) { 1147 ; CHECK-LABEL: orr64imm4s_lsl0: 1148 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}} 1149 %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735> 1150 ret <2 x i64> %tmp1 1151 } 1152 1153 define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) { 1154 ; CHECK-LABEL: orr64imm4s_lsl8: 1155 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #8 1156 %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160> 1157 ret <2 x i64> %tmp1 1158 } 1159 1160 define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) { 1161 ; CHECK-LABEL: orr64imm4s_lsl16: 1162 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #16 1163 %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960> 1164 ret <2 x i64> %tmp1 1165 } 1166 1167 define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) { 1168 ; CHECK-LABEL: orr64imm4s_lsl24: 1169 ; CHECK: orr {{v[0-9]+}}.4s, #{{0xff|255}}, lsl #24 1170 %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856> 1171 ret <2 x i64> %tmp1 1172 } 1173 1174 define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) { 1175 ; CHECK-LABEL: orr8imm4h_lsl0: 1176 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}} 1177 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> 1178 ret <8 x i8> %tmp1 1179 } 1180 1181 define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) { 1182 ; CHECK-LABEL: orr8imm4h_lsl8: 1183 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 1184 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 1185 ret <8 x i8> %tmp1 1186 } 1187 1188 define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) { 1189 ; CHECK-LABEL: orr16imm4h_lsl0: 1190 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}} 1191 %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935> 1192 ret <2 x i32> %tmp1 1193 } 1194 1195 define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) { 1196 ; CHECK-LABEL: orr16imm4h_lsl8: 1197 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 1198 %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360> 1199 ret <2 x i32> %tmp1 1200 } 1201 1202 define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) { 1203 ; CHECK-LABEL: orr64imm4h_lsl0: 1204 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}} 1205 %tmp1 = or <1 x i64> %a, < i64 71777214294589695> 1206 ret <1 x i64> %tmp1 1207 } 1208 1209 define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) { 1210 ; CHECK-LABEL: orr64imm4h_lsl8: 1211 ; CHECK: orr {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8 1212 %tmp1 = or <1 x i64> %a, < i64 -71777214294589696> 1213 ret <1 x i64> %tmp1 1214 } 1215 1216 define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) { 1217 ; CHECK-LABEL: orr8imm8h_lsl0: 1218 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}} 1219 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0> 1220 ret <16 x i8> %tmp1 1221 } 1222 1223 define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) { 1224 ; CHECK-LABEL: orr8imm8h_lsl8: 1225 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 1226 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255> 1227 ret <16 x i8> %tmp1 1228 } 1229 1230 define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) { 1231 ; CHECK-LABEL: orr16imm8h_lsl0: 1232 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}} 1233 %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935> 1234 ret <4 x i32> %tmp1 1235 } 1236 1237 define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) { 1238 ; CHECK-LABEL: orr16imm8h_lsl8: 1239 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 1240 %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360> 1241 ret <4 x i32> %tmp1 1242 } 1243 1244 define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) { 1245 ; CHECK-LABEL: orr64imm8h_lsl0: 1246 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}} 1247 %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695> 1248 ret <2 x i64> %tmp1 1249 } 1250 1251 define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) { 1252 ; CHECK-LABEL: orr64imm8h_lsl8: 1253 ; CHECK: orr {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8 1254 %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696> 1255 ret <2 x i64> %tmp1 1256 } 1257 1258
