1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s 2 3 ; A vector TruncStore can not be selected. 4 ; Test a trunc IR and a vector store IR can be selected correctly. 5 define void @truncStore.v2i64(<2 x i64> %a, <2 x i32>* %result) { 6 ; CHECK-LABEL: truncStore.v2i64: 7 ; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d 8 ; CHECK: {{st1 { v[0-9]+.2s }|str d[0-9]+}}, [x{{[0-9]+|sp}}] 9 %b = trunc <2 x i64> %a to <2 x i32> 10 store <2 x i32> %b, <2 x i32>* %result 11 ret void 12 } 13 14 define void @truncStore.v4i32(<4 x i32> %a, <4 x i16>* %result) { 15 ; CHECK-LABEL: truncStore.v4i32: 16 ; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s 17 ; CHECK: {{st1 { v[0-9]+.4h }|str d[0-9]+}}, [x{{[0-9]+|sp}}] 18 %b = trunc <4 x i32> %a to <4 x i16> 19 store <4 x i16> %b, <4 x i16>* %result 20 ret void 21 } 22 23 define void @truncStore.v4i8(<4 x i32> %a, <4 x i8>* %result) { 24 ; CHECK-LABEL: truncStore.v4i8: 25 ; CHECK: xtn [[TMP:(v[0-9]+)]].4h, v{{[0-9]+}}.4s 26 ; CHECK-NEXT: xtn [[TMP2:(v[0-9]+)]].8b, [[TMP]].8h 27 ; CHECK-NEXT: str s{{[0-9]+}}, [x{{[0-9]+}}] 28 %b = trunc <4 x i32> %a to <4 x i8> 29 store <4 x i8> %b, <4 x i8>* %result 30 ret void 31 } 32 33 define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) { 34 ; CHECK-LABEL: truncStore.v8i16: 35 ; CHECK: xtn v{{[0-9]+}}.8b, v{{[0-9]+}}.8h 36 ; CHECK: {{st1 { v[0-9]+.8b }|str d[0-9]+}}, [x{{[0-9]+|sp}}] 37 %b = trunc <8 x i16> %a to <8 x i8> 38 store <8 x i8> %b, <8 x i8>* %result 39 ret void 40 } 41 42 ; A vector LoadExt can not be selected. 43 ; Test a vector load IR and a sext/zext IR can be selected correctly. 44 define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) { 45 ; CHECK-LABEL: loadSExt.v4i8: 46 ; CHECK: ldrsb 47 %a = load <4 x i8>, <4 x i8>* %ref 48 %conv = sext <4 x i8> %a to <4 x i32> 49 ret <4 x i32> %conv 50 } 51 52 define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) { 53 ; CHECK-LABEL: loadZExt.v4i8: 54 ; CHECK: ldrb 55 %a = load <4 x i8>, <4 x i8>* %ref 56 %conv = zext <4 x i8> %a to <4 x i32> 57 ret <4 x i32> %conv 58 } 59 60 define i32 @loadExt.i32(<4 x i8>* %ref) { 61 ; CHECK-LABEL: loadExt.i32: 62 ; CHECK: ldrb 63 %a = load <4 x i8>, <4 x i8>* %ref 64 %vecext = extractelement <4 x i8> %a, i32 0 65 %conv = zext i8 %vecext to i32 66 ret i32 %conv 67 } 68
