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      1 ; RUN: llc -o - %s -mtriple=aarch64-- | FileCheck %s
      2 
      3 ; CHECK-LABEL: and1:
      4 ; CHECK: and {{w[0-9]+}}, w0, #0xfffffffd
      5 
      6 define void @and1(i32 %a, i8* nocapture %p) {
      7 entry:
      8   %and = and i32 %a, 253
      9   %conv = trunc i32 %and to i8
     10   store i8 %conv, i8* %p, align 1
     11   ret void
     12 }
     13 
     14 ; (a & 0x3dfd) | 0xffffc000
     15 ;
     16 ; CHECK-LABEL: and2:
     17 ; CHECK: and {{w[0-9]+}}, w0, #0xfdfdfdfd
     18 
     19 define i32 @and2(i32 %a) {
     20 entry:
     21   %and = and i32 %a, 15869
     22   %or = or i32 %and, -16384
     23   ret i32 %or
     24 }
     25 
     26 ; (a & 0x19) | 0xffffffc0
     27 ;
     28 ; CHECK-LABEL: and3:
     29 ; CHECK: and {{w[0-9]+}}, w0, #0x99999999
     30 
     31 define i32 @and3(i32 %a) {
     32 entry:
     33   %and = and i32 %a, 25
     34   %or = or i32 %and, -64
     35   ret i32 %or
     36 }
     37 
     38 ; (a & 0xc5600) | 0xfff1f1ff
     39 ;
     40 ; CHECK-LABEL: and4:
     41 ; CHECK: and {{w[0-9]+}}, w0, #0xfffc07ff
     42 
     43 define i32 @and4(i32 %a) {
     44 entry:
     45   %and = and i32 %a, 787968
     46   %or = or i32 %and, -921089
     47   ret i32 %or
     48 }
     49 
     50 ; Make sure we don't shrink or optimize an XOR's immediate operand if the
     51 ; immediate is -1. Instruction selection turns (and ((xor $mask, -1), $v0)) into
     52 ; a BIC.
     53 
     54 ; CHECK-LABEL: xor1:
     55 ; CHECK: orr [[R0:w[0-9]+]], wzr, #0x38
     56 ; CHECK: bic {{w[0-9]+}}, [[R0]], w0, lsl #3
     57 
     58 define i32 @xor1(i32 %a) {
     59 entry:
     60   %shl = shl i32 %a, 3
     61   %xor = and i32 %shl, 56
     62   %and = xor i32 %xor, 56
     63   ret i32 %and
     64 }
     65 
     66 ; Check that, when (and %t1, 129) is transformed to (and %t0, 0),
     67 ; (xor %arg, 129) doesn't get transformed to (xor %arg, 0).
     68 ;
     69 ; CHECK-LABEL: PR33100:
     70 ; CHECK: mov w[[R0:[0-9]+]], #129
     71 ; CHECK: eor {{x[0-9]+}}, {{x[0-9]+}}, x[[R0]]
     72 
     73 define i64 @PR33100(i64 %arg) {
     74 entry:
     75   %alloca0 = alloca i64
     76   store i64 8, i64* %alloca0, align 4
     77   %t0 = load i64, i64* %alloca0, align 4
     78   %t1 = shl i64 %arg, %t0
     79   %and0 = and i64 %t1, 129
     80   %xor0 = xor i64 %arg, 129
     81   %t2 = add i64 %and0, %xor0
     82   ret i64 %t2
     83 }
     84