1 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,SI,SICI,SIVI 2 # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,CI,SICI 3 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,VI,SIVI 4 5 # REQUIRES: global-isel 6 7 --- | 8 define amdgpu_kernel void @smrd_imm(i32 addrspace(4)* %const0) { ret void } 9 ... 10 --- 11 12 name: smrd_imm 13 legalized: true 14 regBankSelected: true 15 16 # GCN: body: 17 # GCN: [[PTR:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1 18 19 # Immediate offset: 20 # SICI: S_LOAD_DWORD_IMM [[PTR]], 1, 0 21 # VI: S_LOAD_DWORD_IMM [[PTR]], 4, 0 22 23 # Max immediate offset for SI 24 # SICI: S_LOAD_DWORD_IMM [[PTR]], 255, 0 25 # VI: S_LOAD_DWORD_IMM [[PTR]], 1020, 0 26 27 # Immediate overflow for SI 28 # SI: [[K1024:%[0-9]+]]:sreg_32 = S_MOV_B32 1024 29 # SI: S_LOAD_DWORD_SGPR [[PTR]], [[K1024]], 0 30 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 256, 0 31 # VI: S_LOAD_DWORD_IMM [[PTR]], 1024, 0 32 33 # Max immediate offset for VI 34 # SI: [[K1048572:%[0-9]+]]:sreg_32 = S_MOV_B32 1048572 35 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262143 36 # VI: S_LOAD_DWORD_IMM [[PTR]], 1048572 37 38 # 39 # Immediate overflow for VI 40 # SIVI: [[K1048576:%[0-9]+]]:sreg_32 = S_MOV_B32 1048576 41 # SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K1048576]], 0 42 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 262144, 0 43 44 # Max immediate for CI 45 # SIVI: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4294967292 46 # SIVI: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 3 47 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 48 # SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 49 # SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 50 # SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] 51 # SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 52 # SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 53 # SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] 54 # SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 55 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0 56 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 4294967295, 0 57 58 # Immediate overflow for CI 59 # GCN: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0 60 # GCN: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4 61 # GCN: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 62 # GCN-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 63 # GCN-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 64 # GCN: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] 65 # GCN-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 66 # GCN-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 67 # GCN: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] 68 # GCN: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 69 # GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0 70 71 # Max 32-bit byte offset 72 # SIVI: [[K4294967292:%[0-9]+]]:sreg_32 = S_MOV_B32 4294967292 73 # SIVI: S_LOAD_DWORD_SGPR [[PTR]], [[K4294967292]], 0 74 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741823, 0 75 76 # Overflow 32-bit byte offset 77 # SIVI: [[K_LO:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0 78 # SIVI: [[K_HI:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1 79 # SIVI: [[K:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[K_LO]], %subreg.sub0, [[K_HI]], %subreg.sub1 80 # SIVI-DAG: [[K_SUB0:%[0-9]+]]:sgpr_32 = COPY [[K]].sub0 81 # SIVI-DAG: [[PTR_LO:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub0 82 # SIVI: [[ADD_PTR_LO:%[0-9]+]]:sreg_32 = S_ADD_U32 [[PTR_LO]], [[K_SUB0]] 83 # SIVI-DAG: [[K_SUB1:%[0-9]+]]:sgpr_32 = COPY [[K]].sub1 84 # SIVI-DAG: [[PTR_HI:%[0-9]+]]:sgpr_32 = COPY [[PTR]].sub1 85 # SIVI: [[ADD_PTR_HI:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]] 86 # SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 87 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0 88 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0 89 90 body: | 91 bb.0: 92 liveins: $sgpr0_sgpr1 93 94 %0:sgpr(p4) = COPY $sgpr0_sgpr1 95 96 %1:sgpr(s64) = G_CONSTANT i64 4 97 %2:sgpr(p4) = G_GEP %0, %1 98 %3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0) 99 $sgpr0 = COPY %3 100 101 %4:sgpr(s64) = G_CONSTANT i64 1020 102 %5:sgpr(p4) = G_GEP %0, %4 103 %6:sgpr(s32) = G_LOAD %5 :: (load 4 from %ir.const0) 104 $sgpr0 = COPY %6 105 106 %7:sgpr(s64) = G_CONSTANT i64 1024 107 %8:sgpr(p4) = G_GEP %0, %7 108 %9:sgpr(s32) = G_LOAD %8 :: (load 4 from %ir.const0) 109 $sgpr0 = COPY %9 110 111 %10:sgpr(s64) = G_CONSTANT i64 1048572 112 %11:sgpr(p4) = G_GEP %0, %10 113 %12:sgpr(s32) = G_LOAD %11 :: (load 4 from %ir.const0) 114 $sgpr0 = COPY %12 115 116 %13:sgpr(s64) = G_CONSTANT i64 1048576 117 %14:sgpr(p4) = G_GEP %0, %13 118 %15:sgpr(s32) = G_LOAD %14 :: (load 4 from %ir.const0) 119 $sgpr0 = COPY %15 120 121 %16:sgpr(s64) = G_CONSTANT i64 17179869180 122 %17:sgpr(p4) = G_GEP %0, %16 123 %18:sgpr(s32) = G_LOAD %17 :: (load 4 from %ir.const0) 124 $sgpr0 = COPY %18 125 126 %19:sgpr(s64) = G_CONSTANT i64 17179869184 127 %20:sgpr(p4) = G_GEP %0, %19 128 %21:sgpr(s32) = G_LOAD %20 :: (load 4 from %ir.const0) 129 $sgpr0 = COPY %21 130 131 %22:sgpr(s64) = G_CONSTANT i64 4294967292 132 %23:sgpr(p4) = G_GEP %0, %22 133 %24:sgpr(s32) = G_LOAD %23 :: (load 4 from %ir.const0) 134 $sgpr0 = COPY %24 135 136 %25:sgpr(s64) = G_CONSTANT i64 4294967296 137 %26:sgpr(p4) = G_GEP %0, %25 138 %27:sgpr(s32) = G_LOAD %26 :: (load 4 from %ir.const0) 139 $sgpr0 = COPY %27 140 141 ... 142 --- 143
