1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s 3 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s 4 5 --- | 6 define void @exp_compr_v2f16_s() { 7 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0,half 1.0>, <2 x half> <half 1.0, half 1.0>, i1 0, i1 0) 8 ret void 9 } 10 define void @exp_compr_v2f16_v() { 11 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> <half 1.0,half 1.0>, <2 x half> <half 1.0, half 1.0>, i1 0, i1 0) 12 ret void 13 } 14 15 declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) 16 declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) 17 18 ... 19 20 --- 21 name: exp_compr_v2f16_s 22 legalized: true 23 24 body: | 25 bb.0: 26 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 27 ; CHECK-LABEL: name: exp_compr_v2f16_s 28 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 29 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 30 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 31 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 32 ; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false 33 ; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false 34 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) 35 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) 36 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[C2]](s1), [[C3]](s1) 37 %0:_(s32) = G_CONSTANT i32 0 38 %1:_(s32) = G_CONSTANT i32 0 39 %2:_(s32) = COPY $sgpr0 40 %3:_(s32) = COPY $sgpr1 41 %6:_(s1) = G_CONSTANT i1 0 42 %7:_(s1) = G_CONSTANT i1 0 43 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7 44 ... 45 --- 46 name: exp_compr_v2f16_v 47 legalized: true 48 49 body: | 50 bb.0: 51 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 52 ; CHECK-LABEL: name: exp_compr_v2f16_v 53 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 54 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 55 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 56 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 57 ; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false 58 ; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false 59 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr), [[C]](s32), [[C1]](s32), [[COPY]](s32), [[COPY1]](s32), [[C2]](s1), [[C3]](s1) 60 %0:_(s32) = G_CONSTANT i32 0 61 %1:_(s32) = G_CONSTANT i32 0 62 %2:_(s32) = COPY $vgpr0 63 %3:_(s32) = COPY $vgpr1 64 %6:_(s1) = G_CONSTANT i1 0 65 %7:_(s1) = G_CONSTANT i1 0 66 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.compr.v2f16), %0, %1, %2, %3, %6, %7 67 ... 68
