1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s 3 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s 4 5 # REQUIRES: global-isel 6 7 --- | 8 define void @exp_s() { 9 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 1.0, float 1.0, float 1.0, float 1.0, i1 0, i1 0) 10 ret void 11 } 12 define void @exp_v() { 13 call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 1.0, float 1.0, float 1.0, float 1.0, i1 0, i1 0) 14 ret void 15 } 16 17 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) 18 ... 19 20 --- 21 name: exp_s 22 legalized: true 23 24 body: | 25 bb.0: 26 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 27 ; CHECK-LABEL: name: exp_s 28 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 29 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 30 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 31 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 32 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 33 ; CHECK: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3 34 ; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false 35 ; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false 36 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32) 37 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32) 38 ; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32) 39 ; CHECK: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[COPY3]](s32) 40 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), [[C]](s32), [[C1]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[C2]](s1), [[C3]](s1) 41 %0:_(s32) = G_CONSTANT i32 0 42 %1:_(s32) = G_CONSTANT i32 0 43 %2:_(s32) = COPY $sgpr0 44 %3:_(s32) = COPY $sgpr1 45 %4:_(s32) = COPY $sgpr2 46 %5:_(s32) = COPY $sgpr3 47 %6:_(s1) = G_CONSTANT i1 0 48 %7:_(s1) = G_CONSTANT i1 0 49 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %1, %2, %3, %4, %5, %6, %7 50 ... 51 --- 52 name: exp_v 53 legalized: true 54 55 body: | 56 bb.0: 57 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 58 ; CHECK-LABEL: name: exp_v 59 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 60 ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0 61 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 62 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 63 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2 64 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3 65 ; CHECK: [[C2:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false 66 ; CHECK: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 false 67 ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), [[C]](s32), [[C1]](s32), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[C2]](s1), [[C3]](s1) 68 %0:_(s32) = G_CONSTANT i32 0 69 %1:_(s32) = G_CONSTANT i32 0 70 %2:_(s32) = COPY $vgpr0 71 %3:_(s32) = COPY $vgpr1 72 %4:_(s32) = COPY $vgpr2 73 %5:_(s32) = COPY $vgpr3 74 %6:_(s1) = G_CONSTANT i1 0 75 %7:_(s1) = G_CONSTANT i1 0 76 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp.f32), %0, %1, %2, %3, %4, %5, %6, %7 77 ... 78
