1 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GCN %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s 3 4 ; FIXME: Need to handle non-uniform case for function below (load without gep). 5 ; GCN-LABEL: {{^}}v_test_add_v2i16: 6 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 7 8 ; FIXME: or should be unnecessary 9 ; VI: v_add_u16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} 10 ; VI: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 11 ; VI: v_or_b32 12 define amdgpu_kernel void @v_test_add_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { 13 %tid = call i32 @llvm.amdgcn.workitem.id.x() 14 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid 15 %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid 16 %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid 17 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 18 %b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 19 %add = add <2 x i16> %a, %b 20 store <2 x i16> %add, <2 x i16> addrspace(1)* %out 21 ret void 22 } 23 24 ; GCN-LABEL: {{^}}s_test_add_v2i16: 25 ; GFX9: s_load_dword [[VAL0:s[0-9]+]] 26 ; GFX9: s_load_dword [[VAL1:s[0-9]+]] 27 ; GFX9: v_mov_b32_e32 [[VVAL1:v[0-9]+]] 28 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL0]], [[VVAL1]] 29 30 ; VI: s_add_i32 31 ; VI: s_add_i32 32 define amdgpu_kernel void @s_test_add_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %in0, <2 x i16> addrspace(4)* %in1) #1 { 33 %a = load <2 x i16>, <2 x i16> addrspace(4)* %in0 34 %b = load <2 x i16>, <2 x i16> addrspace(4)* %in1 35 %add = add <2 x i16> %a, %b 36 store <2 x i16> %add, <2 x i16> addrspace(1)* %out 37 ret void 38 } 39 40 ; GCN-LABEL: {{^}}s_test_add_self_v2i16: 41 ; GFX9: s_load_dword [[VAL:s[0-9]+]] 42 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL]], [[VAL]] 43 44 ; VI: s_add_i32 45 ; VI: s_add_i32 46 define amdgpu_kernel void @s_test_add_self_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %in0) #1 { 47 %a = load <2 x i16>, <2 x i16> addrspace(4)* %in0 48 %add = add <2 x i16> %a, %a 49 store <2 x i16> %add, <2 x i16> addrspace(1)* %out 50 ret void 51 } 52 53 ; FIXME: VI should not scalarize arg access. 54 ; GCN-LABEL: {{^}}s_test_add_v2i16_kernarg: 55 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} 56 57 ; VI: s_add_i32 58 ; VI: s_add_i32 59 ; VI: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 60 ; VI: s_and_b32 61 ; VI: s_or_b32 62 define amdgpu_kernel void @s_test_add_v2i16_kernarg(<2 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b) #1 { 63 %add = add <2 x i16> %a, %b 64 store <2 x i16> %add, <2 x i16> addrspace(1)* %out 65 ret void 66 } 67 68 ; FIXME: Eliminate or with sdwa 69 ; GCN-LABEL: {{^}}v_test_add_v2i16_constant: 70 ; GFX9: s_mov_b32 [[CONST:s[0-9]+]], 0x1c8007b{{$}} 71 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]] 72 73 ; VI-DAG: v_mov_b32_e32 v[[SCONST:[0-9]+]], 0x1c8 74 ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0x7b, v{{[0-9]+}} 75 ; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v[[SCONST]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 76 ; VI: v_or_b32_e32 77 define amdgpu_kernel void @v_test_add_v2i16_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { 78 %tid = call i32 @llvm.amdgcn.workitem.id.x() 79 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid 80 %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid 81 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 82 %add = add <2 x i16> %a, <i16 123, i16 456> 83 store <2 x i16> %add, <2 x i16> addrspace(1)* %out 84 ret void 85 } 86 87 ; FIXME: Need to handle non-uniform case for function below (load without gep). 88 ; GCN-LABEL: {{^}}v_test_add_v2i16_neg_constant: 89 ; GFX9: s_mov_b32 [[CONST:s[0-9]+]], 0xfc21fcb3{{$}} 90 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[CONST]] 91 92 ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, 0xfffffcb3, v{{[0-9]+}} 93 ; VI-DAG: v_mov_b32_e32 v[[SCONST:[0-9]+]], 0xfffffc21 94 ; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v[[SCONST]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 95 define amdgpu_kernel void @v_test_add_v2i16_neg_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { 96 %tid = call i32 @llvm.amdgcn.workitem.id.x() 97 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid 98 %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid 99 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 100 %add = add <2 x i16> %a, <i16 -845, i16 -991> 101 store <2 x i16> %add, <2 x i16> addrspace(1)* %out 102 ret void 103 } 104 105 ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_neg1: 106 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, -1 op_sel_hi:[1,0]{{$}} 107 108 ; VI: v_mov_b32_e32 v[[SCONST:[0-9]+]], -1 109 ; VI: flat_load_dword [[LOAD:v[0-9]+]] 110 ; VI-DAG: v_add_u16_sdwa v{{[0-9]+}}, [[LOAD]], v[[SCONST]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 111 ; VI-DAG: v_add_u16_e32 v{{[0-9]+}}, -1, [[LOAD]] 112 ; VI: v_or_b32_e32 113 define amdgpu_kernel void @v_test_add_v2i16_inline_neg1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { 114 %tid = call i32 @llvm.amdgcn.workitem.id.x() 115 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid 116 %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid 117 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 118 %add = add <2 x i16> %a, <i16 -1, i16 -1> 119 store <2 x i16> %add, <2 x i16> addrspace(1)* %out 120 ret void 121 } 122 123 ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_lo_zero_hi: 124 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, 32{{$}} 125 126 ; VI: flat_load_dword 127 ; VI-NOT: v_add_u16 128 ; VI: v_and_b32_e32 v{{[0-9]+}}, 0xffff0000, 129 ; VI: v_add_u16_e32 v{{[0-9]+}}, 32, v{{[0-9]+}} 130 ; VI-NOT: v_add_u16 131 ; VI: v_or_b32_e32 132 define amdgpu_kernel void @v_test_add_v2i16_inline_lo_zero_hi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { 133 %tid = call i32 @llvm.amdgcn.workitem.id.x() 134 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid 135 %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid 136 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 137 %add = add <2 x i16> %a, <i16 32, i16 0> 138 store <2 x i16> %add, <2 x i16> addrspace(1)* %out 139 ret void 140 } 141 142 ; The high element gives fp 143 ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_fp_split: 144 ; GFX9: s_mov_b32 [[K:s[0-9]+]], 1.0 145 ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]{{$}} 146 147 ; VI-NOT: v_add_u16 148 ; VI: v_mov_b32_e32 v[[K:[0-9]+]], 0x3f80 149 ; VI: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v[[K]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD 150 ; VI-NOT: v_add_u16 151 ; VI: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD 152 define amdgpu_kernel void @v_test_add_v2i16_inline_fp_split(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { 153 %tid = call i32 @llvm.amdgcn.workitem.id.x() 154 %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid 155 %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid 156 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 157 %add = add <2 x i16> %a, <i16 0, i16 16256> 158 store <2 x i16> %add, <2 x i16> addrspace(1)* %out 159 ret void 160 } 161 162 ; FIXME: Need to handle non-uniform case for function below (load without gep). 163 ; GCN-LABEL: {{^}}v_test_add_v2i16_zext_to_v2i32: 164 ; GFX9: global_load_dword [[A:v[0-9]+]] 165 ; GFX9: global_load_dword [[B:v[0-9]+]] 166 167 ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] 168 ; GFX9-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]] 169 ; GFX9-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] 170 ; GFX9: buffer_store_dwordx2 v{{\[}}[[ELT0]]:[[ELT1]]{{\]}} 171 172 ; VI: flat_load_dword v[[A:[0-9]+]] 173 ; VI: flat_load_dword v[[B:[0-9]+]] 174 175 ; VI-NOT: and 176 ; VI-NOT: shl 177 ; VI: v_add_u16_e32 v[[ADD_LO:[0-9]+]], v[[A]], v[[B]] 178 ; VI: v_add_u16_sdwa v[[ADD_HI:[0-9]+]], v[[A]], v[[B]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 179 ; VI-NOT: and 180 ; VI-NOT: shl 181 ; VI: buffer_store_dwordx2 v{{\[}}[[ADD_LO]]:[[ADD_HI]]{{\]}} 182 define amdgpu_kernel void @v_test_add_v2i16_zext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { 183 %tid = call i32 @llvm.amdgcn.workitem.id.x() 184 %gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid 185 %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid 186 %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid 187 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 188 %b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 189 %add = add <2 x i16> %a, %b 190 %ext = zext <2 x i16> %add to <2 x i32> 191 store <2 x i32> %ext, <2 x i32> addrspace(1)* %out 192 ret void 193 } 194 195 ; FIXME: Need to handle non-uniform case for function below (load without gep). 196 ; GCN-LABEL: {{^}}v_test_add_v2i16_zext_to_v2i64: 197 ; GFX9: global_load_dword [[A:v[0-9]+]] 198 ; GFX9: global_load_dword [[B:v[0-9]+]] 199 200 ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] 201 ; GFX9-DAG: v_and_b32_e32 v[[ELT0:[0-9]+]], 0xffff, [[ADD]] 202 ; GFX9-DAG: v_lshrrev_b32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] 203 ; GFX9: buffer_store_dwordx4 204 205 ; VI-DAG: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}} 206 ; VI: flat_load_dword v[[A:[0-9]+]] 207 ; VI: flat_load_dword v[[B:[0-9]+]] 208 209 ; VI-DAG: v_add_u16_e32 210 ; VI: v_add_u16_sdwa v[[ADD_HI:[0-9]+]], v[[A]], v[[B]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 211 212 ; VI: buffer_store_dwordx4 213 define amdgpu_kernel void @v_test_add_v2i16_zext_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { 214 %tid = call i32 @llvm.amdgcn.workitem.id.x() 215 %gep.out = getelementptr inbounds <2 x i64>, <2 x i64> addrspace(1)* %out, i32 %tid 216 %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid 217 %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid 218 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 219 %b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 220 %add = add <2 x i16> %a, %b 221 %ext = zext <2 x i16> %add to <2 x i64> 222 store <2 x i64> %ext, <2 x i64> addrspace(1)* %out 223 ret void 224 } 225 226 ; FIXME: Need to handle non-uniform case for function below (load without gep). 227 ; GCN-LABEL: {{^}}v_test_add_v2i16_sext_to_v2i32: 228 ; GFX9: global_load_dword [[A:v[0-9]+]] 229 ; GFX9: global_load_dword [[B:v[0-9]+]] 230 231 ; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[A]], [[B]] 232 ; GFX9-DAG: v_bfe_i32 v[[ELT0:[0-9]+]], [[ADD]], 0, 16 233 ; GFX9-DAG: v_ashrrev_i32_e32 v[[ELT1:[0-9]+]], 16, [[ADD]] 234 ; GFX9: buffer_store_dwordx2 v{{\[}}[[ELT0]]:[[ELT1]]{{\]}} 235 236 ; VI: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 237 ; VI: v_add_u16_e32 238 239 ; VI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16 240 ; VI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16 241 ; VI: buffer_store_dwordx2 242 define amdgpu_kernel void @v_test_add_v2i16_sext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { 243 %tid = call i32 @llvm.amdgcn.workitem.id.x() 244 %gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid 245 %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid 246 %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid 247 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 248 %b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 249 %add = add <2 x i16> %a, %b 250 %ext = sext <2 x i16> %add to <2 x i32> 251 store <2 x i32> %ext, <2 x i32> addrspace(1)* %out 252 ret void 253 } 254 255 ; FIXME: Need to handle non-uniform case for function below (load without gep). 256 ; GCN-LABEL: {{^}}v_test_add_v2i16_sext_to_v2i64: 257 ; GCN: {{flat|global}}_load_dword 258 ; GCN: {{flat|global}}_load_dword 259 260 ; GFX9: v_pk_add_u16 261 ; GFX9: v_lshrrev_b32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} 262 263 ; VI: v_add_u16_sdwa 264 ; VI: v_add_u16_e32 265 266 ; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16 267 ; GCN: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16 268 ; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} 269 ; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} 270 define amdgpu_kernel void @v_test_add_v2i16_sext_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { 271 %tid = call i32 @llvm.amdgcn.workitem.id.x() 272 %gep.out = getelementptr inbounds <2 x i64>, <2 x i64> addrspace(1)* %out, i32 %tid 273 %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid 274 %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid 275 %a = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 276 %b = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 277 %add = add <2 x i16> %a, %b 278 %ext = sext <2 x i16> %add to <2 x i64> 279 store <2 x i64> %ext, <2 x i64> addrspace(1)* %out 280 ret void 281 } 282 283 declare i32 @llvm.amdgcn.workitem.id.x() #0 284 285 attributes #0 = { nounwind readnone } 286 attributes #1 = { nounwind } 287
