1 ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2 ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s 4 5 ; This pixel shader does not use the result of its interpolation, so it would 6 ; end up with an interpolation mode set in PSAddr but not PSEnable. This test tests 7 ; the workaround that ensures that an interpolation mode is also set in PSEnable. 8 ; GCN-LABEL: {{^}}amdpal_psenable: 9 ; GCN: .amd_amdgpu_pal_metadata{{.*}}0xa1b3,0x2,0xa1b4,0x2, 10 define amdgpu_ps void @amdpal_psenable(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <2 x float> %pos) #6 { 11 %inst23 = extractelement <2 x float> %pos, i32 0 12 %inst24 = extractelement <2 x float> %pos, i32 1 13 %inst25 = tail call float @llvm.amdgcn.interp.p1(float %inst23, i32 0, i32 0, i32 %m0) 14 %inst26 = tail call float @llvm.amdgcn.interp.p2(float %inst25, float %inst24, i32 0, i32 0, i32 %m0) 15 ret void 16 } 17 18 declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2 19 declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2 20 21 attributes #6 = { nounwind "InitialPSInputAddr"="2" } 22
