1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3 4 ; This used to crash because during intermediate control flow lowering, there 5 ; was a sequence 6 ; s_mov_b64 s[0:1], exec 7 ; s_and_b64 s[2:3], s[0:1], s[2:3] ; def & use of the same register pair 8 ; ... 9 ; s_mov_b64_term exec, s[2:3] 10 ; that was not treated correctly. 11 ; 12 ; GCN-LABEL: {{^}}ham: 13 ; GCN-DAG: v_cmp_lt_f32_e64 [[OTHERCC:s\[[0-9]+:[0-9]+\]]], 14 ; GCN-DAG: v_cmp_lt_f32_e32 vcc, 15 ; GCN: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], vcc, [[OTHERCC]] 16 ; GCN: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[AND]] 17 ; GCN: ; mask branch [[BB5:BB[0-9]+_[0-9]+]] 18 19 ; GCN-NEXT: BB{{[0-9]+_[0-9]+}}: ; %bb4 20 ; GCN: ds_write_b32 21 22 ; GCN: [[BB5]] 23 ; GCN-NEXT: s_endpgm 24 ; GCN-NEXT: .Lfunc_end 25 define amdgpu_ps void @ham(float %arg, float %arg1) #0 { 26 bb: 27 %tmp = fcmp ogt float %arg, 0.000000e+00 28 %tmp2 = fcmp ogt float %arg1, 0.000000e+00 29 %tmp3 = and i1 %tmp, %tmp2 30 br i1 %tmp3, label %bb4, label %bb5 31 32 bb4: ; preds = %bb 33 store volatile i32 4, i32 addrspace(3)* undef 34 unreachable 35 36 bb5: ; preds = %bb 37 ret void 38 } 39 40 attributes #0 = { nounwind readonly "InitialPSInputAddr"="36983" } 41 attributes #1 = { nounwind readnone } 42
