1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s 3 4 ; Make sure we don't crash or assert on spir_kernel calling convention. 5 6 ; GCN-LABEL: {{^}}kernel: 7 ; GCN: s_endpgm 8 define spir_kernel void @kernel(i32 addrspace(1)* %out) { 9 entry: 10 store i32 0, i32 addrspace(1)* %out 11 ret void 12 } 13 14 ; FIXME: This is treated like a kernel 15 ; XGCN-LABEL: {{^}}func: 16 ; XGCN: s_endpgm 17 ; define spir_func void @func(i32 addrspace(1)* %out) { 18 ; entry: 19 ; store i32 0, i32 addrspace(1)* %out 20 ; ret void 21 ; } 22 23 ; GCN-LABEL: {{^}}ps_ret_cc_f16: 24 ; SI: v_cvt_f16_f32_e32 v0, v0 25 ; SI: v_cvt_f32_f16_e32 v0, v0 26 ; SI: v_add_f32_e32 v0, 1.0, v0 27 28 ; VI: v_add_f16_e32 v0, 1.0, v0 29 ; VI: ; return 30 define amdgpu_ps half @ps_ret_cc_f16(half %arg0) { 31 %add = fadd half %arg0, 1.0 32 ret half %add 33 } 34 35 ; GCN-LABEL: {{^}}ps_ret_cc_inreg_f16: 36 ; SI: v_cvt_f16_f32_e32 v0, s0 37 ; SI: v_cvt_f32_f16_e32 v0, v0 38 ; SI: v_add_f32_e32 v0, 1.0, v0 39 40 ; VI: v_add_f16_e64 v0, s0, 1.0 41 ; VI: ; return 42 define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) { 43 %add = fadd half %arg0, 1.0 44 ret half %add 45 } 46 47 ; GCN-LABEL: {{^}}fastcc: 48 ; GCN: v_add_f32_e32 v0, 4.0, v0 49 define fastcc float @fastcc(float %arg0) #0 { 50 %add = fadd float %arg0, 4.0 51 ret float %add 52 } 53 54 ; GCN-LABEL: {{^}}coldcc: 55 ; GCN: v_add_f32_e32 v0, 4.0, v0 56 define coldcc float @coldcc(float %arg0) #0 { 57 %add = fadd float %arg0, 4.0 58 ret float %add 59 } 60 61 ; GCN-LABEL: {{^}}call_coldcc: 62 ; GCN: v_mov_b32_e32 v0, 1.0 63 ; GCN: s_swappc_b64 64 define amdgpu_kernel void @call_coldcc() #0 { 65 %val = call float @coldcc(float 1.0) 66 store float %val, float addrspace(1)* undef 67 ret void 68 } 69 70 ; GCN-LABEL: {{^}}call_fastcc: 71 ; GCN: v_mov_b32_e32 v0, 1.0 72 ; GCN: s_swappc_b64 73 define amdgpu_kernel void @call_fastcc() #0 { 74 %val = call float @fastcc(float 1.0) 75 store float %val, float addrspace(1)* undef 76 ret void 77 } 78 79 ; Mesa compute shader: check for 47176 (COMPUTE_PGM_RSRC1) in .AMDGPU.config 80 ; GCN-LABEL: .AMDGPU.config 81 ; GCN: .long 47176 82 ; GCN-LABEL: {{^}}cs_mesa: 83 define amdgpu_cs half @cs_mesa(half %arg0) { 84 %add = fadd half %arg0, 1.0 85 ret half %add 86 } 87 88 ; Mesa pixel shader: check for 45096 (SPI_SHADER_PGM_RSRC1_PS) in .AMDGPU.config 89 ; GCN-LABEL: .AMDGPU.config 90 ; GCN: .long 45096 91 ; GCN-LABEL: {{^}}ps_mesa: 92 define amdgpu_ps half @ps_mesa(half %arg0) { 93 %add = fadd half %arg0, 1.0 94 ret half %add 95 } 96 97 ; Mesa vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in .AMDGPU.config 98 ; GCN-LABEL: .AMDGPU.config 99 ; GCN: .long 45352 100 ; GCN-LABEL: {{^}}vs_mesa: 101 define amdgpu_vs half @vs_mesa(half %arg0) { 102 %add = fadd half %arg0, 1.0 103 ret half %add 104 } 105 106 ; Mesa geometry shader: check for 45608 (SPI_SHADER_PGM_RSRC1_GS) in .AMDGPU.config 107 ; GCN-LABEL: .AMDGPU.config 108 ; GCN: .long 45608 109 ; GCN-LABEL: {{^}}gs_mesa: 110 define amdgpu_gs half @gs_mesa(half %arg0) { 111 %add = fadd half %arg0, 1.0 112 ret half %add 113 } 114 115 ; Mesa hull shader: check for 46120 (SPI_SHADER_PGM_RSRC1_HS) in .AMDGPU.config 116 ; GCN-LABEL: .AMDGPU.config 117 ; GCN: .long 46120 118 ; GCN-LABEL: {{^}}hs_mesa: 119 define amdgpu_hs half @hs_mesa(half %arg0) { 120 %add = fadd half %arg0, 1.0 121 ret half %add 122 } 123 124 attributes #0 = { nounwind noinline } 125
