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      1 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -O0 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
      2 
      3 ; GCN-LABEL: {{^}}eq_t:
      4 ; GCN-DAG: s_load_dword [[X:s[0-9]+]]
      5 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
      6 ; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], [[ONE]]{{$}}
      7 ; GCN-NOT: 0xddd5
      8 ; GCN-NOT: v_cndmask_b32
      9 ; GCN-NOT: v_cmp_eq_u32
     10 ; GCN-NOT: v_cndmask_b32
     11 ; GCN-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2.0
     12 ; GCN-DAG: v_mov_b32_e32 [[FOUR:v[0-9]+]], 4.0
     13 ; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], [[TWO]], [[FOUR]], [[CC]]
     14 ; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
     15 define amdgpu_kernel void @eq_t(float %x) {
     16   %c1 = fcmp olt float %x, 1.0
     17   %s1 = select i1 %c1, i32 56789, i32 1
     18   %c2 = icmp eq i32 %s1, 56789
     19   %s2 = select i1 %c2, float 4.0, float 2.0
     20   store float %s2, float* undef, align 4
     21   ret void
     22 }
     23 
     24 ; GCN-LABEL: {{^}}ne_t:
     25 ; GCN-DAG: s_load_dword [[X:s[0-9]+]]
     26 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
     27 ; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], [[ONE]]{{$}}
     28 ; GCN-NOT: 0xddd5
     29 ; GCN-NOT: v_cndmask_b32
     30 ; GCN-NOT: v_cmp_eq_u32
     31 ; GCN-NOT: v_cndmask_b32
     32 ; GCN-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2.0
     33 ; GCN-DAG: v_mov_b32_e32 [[FOUR:v[0-9]+]], 4.0
     34 ; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], [[FOUR]], [[TWO]], [[CC]]
     35 ; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
     36 define amdgpu_kernel void @ne_t(float %x) {
     37   %c1 = fcmp olt float %x, 1.0
     38   %s1 = select i1 %c1, i32 56789, i32 1
     39   %c2 = icmp ne i32 %s1, 56789
     40   %s2 = select i1 %c2, float 4.0, float 2.0
     41   store float %s2, float* undef, align 4
     42   ret void
     43 }
     44 
     45 ; GCN-LABEL: {{^}}eq_f:
     46 ; GCN-DAG: s_load_dword [[X:s[0-9]+]]
     47 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
     48 ; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], [[ONE]]{{$}}
     49 ; GCN-NOT: 0xddd5
     50 ; GCN-NOT: v_cndmask_b32
     51 ; GCN-NOT: v_cmp_eq_u32
     52 ; GCN-NOT: v_cndmask_b32
     53 ; GCN-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2.0
     54 ; GCN-DAG: v_mov_b32_e32 [[FOUR:v[0-9]+]], 4.0
     55 ; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], [[FOUR]], [[TWO]], [[CC]]
     56 ; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
     57 define amdgpu_kernel void @eq_f(float %x) {
     58   %c1 = fcmp olt float %x, 1.0
     59   %s1 = select i1 %c1, i32 1, i32 56789
     60   %c2 = icmp eq i32 %s1, 56789
     61   %s2 = select i1 %c2, float 4.0, float 2.0
     62   store float %s2, float* undef, align 4
     63   ret void
     64 }
     65 
     66 ; GCN-LABEL: {{^}}ne_f:
     67 ; GCN-DAG: s_load_dword [[X:s[0-9]+]]
     68 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
     69 ; GCN:     v_cmp_lt_f32_e{{32|64}} [[CC:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], [[ONE]]{{$}}
     70 ; GCN-NOT: 0xddd5
     71 ; GCN-NOT: v_cndmask_b32
     72 ; GCN-NOT: v_cmp_eq_u32
     73 ; GCN-NOT: v_cndmask_b32
     74 ; GCN-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2.0
     75 ; GCN-DAG: v_mov_b32_e32 [[FOUR:v[0-9]+]], 4.0
     76 ; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], [[TWO]], [[FOUR]], [[CC]]
     77 ; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
     78 define amdgpu_kernel void @ne_f(float %x) {
     79   %c1 = fcmp olt float %x, 1.0
     80   %s1 = select i1 %c1, i32 1, i32 56789
     81   %c2 = icmp ne i32 %s1, 56789
     82   %s2 = select i1 %c2, float 4.0, float 2.0
     83   store float %s2, float* undef, align 4
     84   ret void
     85 }
     86 
     87 ; GCN-LABEL: {{^}}different_constants:
     88 ; GCN-DAG: s_load_dword [[X:s[0-9]+]]
     89 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.0
     90 ; GCN-DAG: v_cmp_lt_f32_e{{32|64}} [[CC1:s\[[0-9]+:[0-9]+\]|vcc]], [[X]], [[ONE]]{{$}}
     91 ; GCN-DAG: v_cndmask_b32_e{{32|64}} [[CND1:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}, [[CC1]]
     92 ; GCN-DAG: v_cmp_eq_u32_e{{32|64}} [[CC2:s\[[0-9]+:[0-9]+\]|vcc]], v{{[0-9]+}}, v{{[0-9]+}}{{$}}
     93 ; GCN-DAG: v_mov_b32_e32 [[TWO:v[0-9]+]], 2.0
     94 ; GCN-DAG: v_mov_b32_e32 [[FOUR:v[0-9]+]], 4.0
     95 ; GCN:     v_cndmask_b32_e{{32|64}} [[RES:v[0-9]+]], [[TWO]], [[FOUR]], [[CC2]]
     96 ; GCN:     store_dword v[{{[0-9:]+}}], [[RES]]{{$}}
     97 define amdgpu_kernel void @different_constants(float %x) {
     98   %c1 = fcmp olt float %x, 1.0
     99   %s1 = select i1 %c1, i32 56789, i32 1
    100   %c2 = icmp eq i32 %s1, 5678
    101   %s2 = select i1 %c2, float 4.0, float 2.0
    102   store float %s2, float* undef, align 4
    103   ret void
    104 }
    105