1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s 2 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s 3 4 declare i32 @llvm.amdgcn.workitem.id.x() #0 5 6 @lds.obj = addrspace(3) global [256 x i32] undef, align 4 7 8 ; GCN-LABEL: {{^}}write_ds_sub0_offset0_global: 9 ; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v0 10 ; CI: v_sub_i32_e32 [[BASEPTR:v[0-9]+]], vcc, 0, [[SHL]] 11 ; GFX9: v_sub_u32_e32 [[BASEPTR:v[0-9]+]], 0, [[SHL]] 12 ; GCN: v_mov_b32_e32 [[VAL:v[0-9]+]], 0x7b 13 ; GCN: ds_write_b32 [[BASEPTR]], [[VAL]] offset:12 14 define amdgpu_kernel void @write_ds_sub0_offset0_global() #0 { 15 entry: 16 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1 17 %sub1 = sub i32 0, %x.i 18 %tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1 19 %arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3 20 store i32 123, i32 addrspace(3)* %arrayidx 21 ret void 22 } 23 24 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset: 25 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 26 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 27 ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] 28 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 29 ; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535 30 define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 { 31 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 32 %neg = sub i32 0, %x.i 33 %shl = shl i32 %neg, 2 34 %add = add i32 65535, %shl 35 %ptr = inttoptr i32 %add to i8 addrspace(3)* 36 store i8 13, i8 addrspace(3)* %ptr 37 ret void 38 } 39 40 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_max_offset_p1: 41 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 42 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x10000, [[SCALED]] 43 ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x10000, [[SCALED]] 44 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 45 ; GCN: ds_write_b8 [[NEG]], [[K]]{{$}} 46 define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_p1() #1 { 47 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 48 %neg = sub i32 0, %x.i 49 %shl = shl i32 %neg, 2 50 %add = add i32 65536, %shl 51 %ptr = inttoptr i32 %add to i8 addrspace(3)* 52 store i8 13, i8 addrspace(3)* %ptr 53 ret void 54 } 55 56 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use: 57 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 58 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 59 ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] 60 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 61 ; GCN-NOT: v_sub 62 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} 63 ; GCN-NOT: v_sub 64 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:456{{$}} 65 ; GCN: s_endpgm 66 define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use() #1 { 67 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 68 %neg = sub i32 0, %x.i 69 %shl = shl i32 %neg, 2 70 %add0 = add i32 123, %shl 71 %add1 = add i32 456, %shl 72 %ptr0 = inttoptr i32 %add0 to i32 addrspace(3)* 73 store volatile i32 13, i32 addrspace(3)* %ptr0 74 %ptr1 = inttoptr i32 %add1 to i32 addrspace(3)* 75 store volatile i32 13, i32 addrspace(3)* %ptr1 76 ret void 77 } 78 79 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_multi_use_same_offset: 80 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 81 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 82 ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] 83 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 84 ; GCN-NOT: v_sub 85 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} 86 ; GCN-NOT: v_sub 87 ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} 88 ; GCN: s_endpgm 89 define amdgpu_kernel void @add_x_shl_neg_to_sub_multi_use_same_offset() #1 { 90 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 91 %neg = sub i32 0, %x.i 92 %shl = shl i32 %neg, 2 93 %add = add i32 123, %shl 94 %ptr = inttoptr i32 %add to i32 addrspace(3)* 95 store volatile i32 13, i32 addrspace(3)* %ptr 96 store volatile i32 13, i32 addrspace(3)* %ptr 97 ret void 98 } 99 100 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset: 101 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 102 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] 103 ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0, [[SCALED]] 104 ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset0:254 offset1:255 105 define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 { 106 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 107 %neg = sub i32 0, %x.i 108 %shl = shl i32 %neg, 2 109 %add = add i32 1019, %shl 110 %ptr = inttoptr i32 %add to i64 addrspace(3)* 111 store i64 123, i64 addrspace(3)* %ptr, align 4 112 ret void 113 } 114 115 ; GCN-LABEL: {{^}}add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1: 116 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALED:v[0-9]+]], 2, v0 117 ; CI-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]] 118 ; GFX9-DAG: v_sub_u32_e32 [[NEG:v[0-9]+]], 0x3fc, [[SCALED]] 119 ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}} 120 define amdgpu_kernel void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #1 { 121 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 122 %neg = sub i32 0, %x.i 123 %shl = shl i32 %neg, 2 124 %add = add i32 1020, %shl 125 %ptr = inttoptr i32 %add to i64 addrspace(3)* 126 store i64 123, i64 addrspace(3)* %ptr, align 4 127 ret void 128 } 129 130 attributes #0 = { nounwind readnone } 131 attributes #1 = { nounwind } 132 attributes #2 = { nounwind convergent } 133
