1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s 2 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s 3 4 @lds = addrspace(3) global [512 x float] undef, align 4 5 6 ; GCN-LABEL: @simple_write2st64_one_val_f32_0_1 7 ; CI-DAG: s_mov_b32 m0 8 ; GFX9-NOT: m0n 9 10 ; GCN-DAG: {{buffer|global}}_load_dword [[VAL:v[0-9]+]] 11 ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 12 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:1 13 ; GCN: s_endpgm 14 define amdgpu_kernel void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float addrspace(1)* %in) #0 { 15 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 16 %in.gep = getelementptr float, float addrspace(1)* %in, i32 %x.i 17 %val = load float, float addrspace(1)* %in.gep, align 4 18 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 19 store float %val, float addrspace(3)* %arrayidx0, align 4 20 %add.x = add nsw i32 %x.i, 64 21 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 22 store float %val, float addrspace(3)* %arrayidx1, align 4 23 ret void 24 } 25 26 ; GCN-LABEL: @simple_write2st64_two_val_f32_2_5 27 ; CI-DAG: s_mov_b32 m0 28 ; GFX9-NOT: m0 29 30 ; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 31 ; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 32 33 ; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, off{{$}} 34 ; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, off offset:4 35 36 37 ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 38 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 39 ; GCN: s_endpgm 40 define amdgpu_kernel void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float addrspace(1)* %in) #0 { 41 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 42 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i 43 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 44 %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 45 %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 46 %add.x.0 = add nsw i32 %x.i, 128 47 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0 48 store float %val0, float addrspace(3)* %arrayidx0, align 4 49 %add.x.1 = add nsw i32 %x.i, 320 50 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1 51 store float %val1, float addrspace(3)* %arrayidx1, align 4 52 ret void 53 } 54 55 ; GCN-LABEL: @simple_write2st64_two_val_max_offset_f32 56 ; CI-DAG: s_mov_b32 m0 57 ; GFX9-NOT: m0 58 59 ; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 60 ; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 61 62 ; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, off{{$}} 63 ; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, off offset:4 64 65 ; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v{{[0-9]+}} 66 ; GCN: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]] 67 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255 68 ; GCN: s_endpgm 69 define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 { 70 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 71 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i 72 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 73 %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 74 %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 75 %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i 76 store float %val0, float addrspace(3)* %arrayidx0, align 4 77 %add.x = add nsw i32 %x.i, 16320 78 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x 79 store float %val1, float addrspace(3)* %arrayidx1, align 4 80 ret void 81 } 82 83 ; GCN-LABEL: @simple_write2st64_two_val_max_offset_f64 84 ; CI-DAG: s_mov_b32 m0 85 ; GFX9-NOT: m0 86 87 ; CI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 88 ; CI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 89 90 ; GFX9-DAG: global_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, off{{$}} 91 ; GFX9-DAG: global_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, off offset:8 92 93 ; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 3, v{{[0-9]+}} 94 ; GCN: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]] 95 ; GCN: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 96 ; GCN: s_endpgm 97 define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { 98 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 99 %in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i 100 %in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1 101 %val0 = load volatile double, double addrspace(1)* %in.gep.0, align 8 102 %val1 = load volatile double, double addrspace(1)* %in.gep.1, align 8 103 %add.x.0 = add nsw i32 %x.i, 256 104 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0 105 store double %val0, double addrspace(3)* %arrayidx0, align 8 106 %add.x.1 = add nsw i32 %x.i, 8128 107 %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1 108 store double %val1, double addrspace(3)* %arrayidx1, align 8 109 ret void 110 } 111 112 ; GCN-LABEL: @byte_size_only_divisible_64_write2st64_f64 113 ; CI-DAG: s_mov_b32 m0 114 ; GFX9-NOT: m0 115 116 ; GCN-NOT: ds_write2st64_b64 117 ; GCN: ds_write2_b64 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:8 118 ; GCN: s_endpgm 119 define amdgpu_kernel void @byte_size_only_divisible_64_write2st64_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { 120 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 121 %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i 122 %val = load double, double addrspace(1)* %in.gep, align 8 123 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i 124 store double %val, double addrspace(3)* %arrayidx0, align 8 125 %add.x = add nsw i32 %x.i, 8 126 %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x 127 store double %val, double addrspace(3)* %arrayidx1, align 8 128 ret void 129 } 130 131 declare i32 @llvm.amdgcn.workitem.id.x() #1 132 declare i32 @llvm.amdgcn.workitem.id.y() #1 133 134 attributes #0 = { nounwind } 135 attributes #1 = { nounwind readnone } 136 attributes #2 = { convergent nounwind } 137
