1 ; RUN: llc -march=amdgcn -enable-no-signed-zeros-fp-math=0 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-SAFE %s 2 ; RUN: llc -march=amdgcn -enable-no-signed-zeros-fp-math=1 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-UNSAFE %s 3 ; RUN: llc -march=amdgcn -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-UNSAFE %s 4 5 declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone 6 7 ; Test that the -enable-no-signed-zeros-fp-math flag works 8 9 ; GCN-LABEL: {{^}}fneg_fsub_f32: 10 ; GCN: v_sub_f32_e32 [[SUB:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}} 11 ; GCN-SAFE: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[SUB]] 12 13 ; GCN-UNSAFE-NOT: xor 14 define amdgpu_kernel void @fneg_fsub_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { 15 %tid = call i32 @llvm.amdgcn.workitem.id.x() 16 %add = add i32 %tid, 1 17 %gep = getelementptr float, float addrspace(1)* %in, i32 %tid 18 %b_ptr = getelementptr float, float addrspace(1)* %in, i32 %add 19 %a = load float, float addrspace(1)* %gep, align 4 20 %b = load float, float addrspace(1)* %b_ptr, align 4 21 %result = fsub float %a, %b 22 %neg.result = fsub float -0.0, %result 23 store float %neg.result, float addrspace(1)* %out, align 4 24 ret void 25 } 26 27 attributes #0 = { nounwind } 28
