1 # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s 2 3 # GCN-LABEL: name: kill_all 4 # GCN: bb.0: 5 # GCN-NEXT: S_ENDPGM 6 name: kill_all 7 tracksRegLiveness: true 8 registers: 9 - { id: 0, class: vreg_64 } 10 - { id: 1, class: vgpr_32 } 11 - { id: 2, class: vgpr_32 } 12 - { id: 3, class: sgpr_32 } 13 - { id: 4, class: sgpr_32 } 14 body: | 15 bb.0: 16 $vcc = IMPLICIT_DEF 17 %0 = IMPLICIT_DEF 18 %3 = IMPLICIT_DEF 19 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 20 %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4) 21 %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec 22 %4 = S_ADD_U32 %3, 1, implicit-def $scc 23 S_ENDPGM 24 ... 25 --- 26 # GCN-LABEL: name: load_without_memoperand 27 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 28 # GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr 29 # GCN-NEXT: S_ENDPGM 30 name: load_without_memoperand 31 tracksRegLiveness: true 32 registers: 33 - { id: 0, class: vreg_64 } 34 - { id: 1, class: vgpr_32 } 35 - { id: 2, class: vgpr_32 } 36 - { id: 3, class: sgpr_32 } 37 - { id: 4, class: sgpr_32 } 38 body: | 39 bb.0: 40 $vcc = IMPLICIT_DEF 41 %0 = IMPLICIT_DEF 42 %3 = IMPLICIT_DEF 43 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 44 %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr 45 %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec 46 %4 = S_ADD_U32 %3, 1, implicit-def $scc 47 S_ENDPGM 48 ... 49 --- 50 # GCN-LABEL: name: load_volatile 51 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 52 # GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4) 53 # GCN-NEXT: S_ENDPGM 54 name: load_volatile 55 tracksRegLiveness: true 56 registers: 57 - { id: 0, class: vreg_64 } 58 - { id: 1, class: vgpr_32 } 59 - { id: 2, class: vgpr_32 } 60 - { id: 3, class: sgpr_32 } 61 - { id: 4, class: sgpr_32 } 62 body: | 63 bb.0: 64 $vcc = IMPLICIT_DEF 65 %0 = IMPLICIT_DEF 66 %3 = IMPLICIT_DEF 67 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 68 %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4) 69 %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec 70 %4 = S_ADD_U32 %3, 1, implicit-def $scc 71 S_ENDPGM 72 ... 73 --- 74 # GCN-LABEL: name: store 75 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 76 # GCN-NEXT: FLAT_STORE_DWORD %0, %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) 77 # GCN-NEXT: S_ENDPGM 78 name: store 79 tracksRegLiveness: true 80 registers: 81 - { id: 0, class: vreg_64 } 82 - { id: 1, class: vgpr_32 } 83 body: | 84 bb.0: 85 $vcc = IMPLICIT_DEF 86 %0 = IMPLICIT_DEF 87 %1 = IMPLICIT_DEF 88 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 89 FLAT_STORE_DWORD %0, %1, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4) 90 S_ENDPGM 91 ... 92 --- 93 # GCN-LABEL: name: barrier 94 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 95 # GCN-NEXT: S_BARRIER 96 # GCN-NEXT: S_ENDPGM 97 name: barrier 98 tracksRegLiveness: true 99 body: | 100 bb.0: 101 $vcc = IMPLICIT_DEF 102 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 103 S_BARRIER 104 S_ENDPGM 105 ... 106 --- 107 # GCN-LABEL: name: call 108 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 109 # GCN-NEXT: $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3 110 # GCN-NEXT: S_ENDPGM 111 name: call 112 tracksRegLiveness: true 113 body: | 114 bb.0: 115 $vcc = IMPLICIT_DEF 116 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 117 $sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3 118 S_ENDPGM 119 ... 120 --- 121 # GCN-LABEL: name: exp 122 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 123 # GCN-NEXT: EXP 32, undef %0:vgpr_32, undef %1:vgpr_32, %2, undef %3:vgpr_32, 0, 0, 15, implicit $exec 124 # GCN-NEXT: S_ENDPGM 125 name: exp 126 tracksRegLiveness: true 127 registers: 128 - { id: 0, class: vgpr_32 } 129 - { id: 1, class: vgpr_32 } 130 - { id: 2, class: vgpr_32 } 131 - { id: 3, class: vgpr_32 } 132 body: | 133 bb.0: 134 $vcc = IMPLICIT_DEF 135 %2 = IMPLICIT_DEF 136 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 137 EXP 32, undef %0, undef %1, killed %2, undef %3, 0, 0, 15, implicit $exec 138 S_ENDPGM 139 ... 140 --- 141 # GCN-LABEL: name: return_to_epilog 142 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 143 # GCN-NEXT: SI_RETURN_TO_EPILOG killed $vgpr0 144 name: return_to_epilog 145 tracksRegLiveness: true 146 body: | 147 bb.0: 148 $vcc = IMPLICIT_DEF 149 $vgpr0 = IMPLICIT_DEF 150 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 151 SI_RETURN_TO_EPILOG killed $vgpr0 152 ... 153 --- 154 # GCN-LABEL: name: split_block 155 # GCN: bb.0: 156 # GCN-NEXT: successors: %bb.1 157 # GCN-NOT: S_OR_B64 158 # GCN: bb.1: 159 # GCN-NEXT: S_ENDPGM 160 name: split_block 161 tracksRegLiveness: true 162 registers: 163 - { id: 0, class: vgpr_32 } 164 - { id: 1, class: vgpr_32 } 165 - { id: 2, class: sgpr_32 } 166 - { id: 3, class: sgpr_32 } 167 body: | 168 bb.0: 169 $vcc = IMPLICIT_DEF 170 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 171 172 bb.1: 173 %0 = IMPLICIT_DEF 174 %2 = IMPLICIT_DEF 175 %1 = V_ADD_F32_e64 0, killed %0, 0, 1, 0, 0, implicit $exec 176 %3 = S_ADD_U32 %2, 1, implicit-def $scc 177 S_ENDPGM 178 ... 179 --- 180 # GCN-LABEL: name: split_block_empty_block 181 # GCN: bb.0: 182 # GCN-NEXT: successors: %bb.1 183 # GCN-NOT: S_OR_B64 184 # GCN: bb.1: 185 # GCN: bb.2: 186 # GCN-NEXT: S_ENDPGM 187 name: split_block_empty_block 188 tracksRegLiveness: true 189 body: | 190 bb.0: 191 $vcc = IMPLICIT_DEF 192 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 193 194 bb.1: 195 196 bb.2: 197 S_ENDPGM 198 ... 199 --- 200 # GCN-LABEL: name: split_block_uncond_branch 201 # GCN: bb.0: 202 # GCN-NEXT: successors: %bb.1 203 # GCN: S_BRANCH %bb.1 204 # GCN-NOT: S_OR_B64 205 # GCN: bb.1: 206 # GCN-NEXT: S_ENDPGM 207 name: split_block_uncond_branch 208 tracksRegLiveness: true 209 body: | 210 bb.0: 211 $vcc = IMPLICIT_DEF 212 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 213 S_BRANCH %bb.1 214 215 bb.1: 216 S_ENDPGM 217 ... 218 --- 219 # GCN-LABEL: name: split_block_cond_branch 220 # GCN: bb.0: 221 # GCN-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000) 222 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, $vcc, implicit-def $scc 223 # GCN: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc 224 # GCN: bb.1: 225 # GCN: bb.2: 226 # GCN-NEXT: S_ENDPGM 227 name: split_block_cond_branch 228 tracksRegLiveness: true 229 body: | 230 bb.0: 231 $vcc = IMPLICIT_DEF 232 $sgpr0_sgpr1 = S_OR_B64 $exec, $vcc, implicit-def $scc 233 S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc 234 235 bb.1: 236 237 bb.2: 238 S_ENDPGM 239 ... 240 --- 241 # GCN-LABEL: name: two_preds_both_dead 242 # GCN: bb.0: 243 # GCN-NEXT: successors: %bb.2 244 # GCN-NOT: S_OR 245 # GCN: S_BRANCH %bb.2 246 # GCN: bb.1: 247 # GCN-NEXT: successors: %bb.2 248 # GCN-NOT: S_AND 249 # GCN: S_BRANCH %bb.2 250 # GCN: bb.2: 251 # GCN-NEXT: S_ENDPGM 252 name: two_preds_both_dead 253 tracksRegLiveness: true 254 body: | 255 bb.0: 256 $vcc = IMPLICIT_DEF 257 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 258 S_BRANCH %bb.2 259 260 bb.1: 261 $vcc = IMPLICIT_DEF 262 $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc 263 S_BRANCH %bb.2 264 265 bb.2: 266 S_ENDPGM 267 ... 268 --- 269 # GCN-LABEL: name: two_preds_one_dead 270 # GCN: bb.0: 271 # GCN-NEXT: successors: %bb.2 272 # GCN: $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 273 # GCN-NEXT: S_BARRIER 274 # GCN-NEXT: S_BRANCH %bb.2 275 # GCN: bb.1: 276 # GCN-NEXT: successors: %bb.2 277 # GCN-NOT: S_AND 278 # GCN: S_BRANCH %bb.2 279 # GCN: bb.2: 280 # GCN-NEXT: S_ENDPGM 281 name: two_preds_one_dead 282 tracksRegLiveness: true 283 body: | 284 bb.0: 285 $vcc = IMPLICIT_DEF 286 $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc 287 S_BARRIER 288 S_BRANCH %bb.2 289 290 bb.1: 291 $vcc = IMPLICIT_DEF 292 $sgpr0_sgpr1 = S_AND_B64 $exec, killed $vcc, implicit-def $scc 293 S_BRANCH %bb.2 294 295 bb.2: 296 S_ENDPGM 297 ... 298
