1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI -check-prefix=FUNC %s 2 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s 3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s 4 5 declare double @llvm.ceil.f64(double) nounwind readnone 6 declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone 7 declare <3 x double> @llvm.ceil.v3f64(<3 x double>) nounwind readnone 8 declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone 9 declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone 10 declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone 11 12 ; FUNC-LABEL: {{^}}fceil_f64: 13 ; CI: v_ceil_f64_e32 14 ; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014 15 ; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 16 ; FIXME: We should be using s_addk_i32 here, but the reg allocation hints 17 ; are not always followed. 18 ; SI-DAG: s_add_i32 [[SEXP0:s[0-9]+]], [[SEXP]], 0xfffffc01 19 ; SI-DAG: s_lshr_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], [[SEXP0]] 20 ; SI-DAG: s_not_b64 21 ; SI-DAG: s_and_b64 22 ; SI-DAG: cmp_gt_i32 23 ; SI-DAG: cndmask_b32 24 ; SI-DAG: cndmask_b32 25 ; SI-DAG: cmp_lt_i32 26 ; SI-DAG: cndmask_b32 27 ; SI-DAG: cndmask_b32 28 ; SI-DAG: v_cmp_gt_f64 29 ; SI-DAG: v_cmp_lg_f64 30 ; SI-DAG: v_cndmask_b32 31 ; SI: v_cndmask_b32 32 ; SI: v_add_f64 33 ; SI: s_endpgm 34 define amdgpu_kernel void @fceil_f64(double addrspace(1)* %out, double %x) { 35 %y = call double @llvm.ceil.f64(double %x) nounwind readnone 36 store double %y, double addrspace(1)* %out 37 ret void 38 } 39 40 ; FUNC-LABEL: {{^}}fceil_v2f64: 41 ; CI: v_ceil_f64_e32 42 ; CI: v_ceil_f64_e32 43 define amdgpu_kernel void @fceil_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { 44 %y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone 45 store <2 x double> %y, <2 x double> addrspace(1)* %out 46 ret void 47 } 48 49 ; FIXME-FUNC-LABEL: {{^}}fceil_v3f64: 50 ; FIXME-CI: v_ceil_f64_e32 51 ; FIXME-CI: v_ceil_f64_e32 52 ; FIXME-CI: v_ceil_f64_e32 53 ; define amdgpu_kernel void @fceil_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) { 54 ; %y = call <3 x double> @llvm.ceil.v3f64(<3 x double> %x) nounwind readnone 55 ; store <3 x double> %y, <3 x double> addrspace(1)* %out 56 ; ret void 57 ; } 58 59 ; FUNC-LABEL: {{^}}fceil_v4f64: 60 ; CI: v_ceil_f64_e32 61 ; CI: v_ceil_f64_e32 62 ; CI: v_ceil_f64_e32 63 ; CI: v_ceil_f64_e32 64 define amdgpu_kernel void @fceil_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) { 65 %y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone 66 store <4 x double> %y, <4 x double> addrspace(1)* %out 67 ret void 68 } 69 70 ; FUNC-LABEL: {{^}}fceil_v8f64: 71 ; CI: v_ceil_f64_e32 72 ; CI: v_ceil_f64_e32 73 ; CI: v_ceil_f64_e32 74 ; CI: v_ceil_f64_e32 75 ; CI: v_ceil_f64_e32 76 ; CI: v_ceil_f64_e32 77 ; CI: v_ceil_f64_e32 78 ; CI: v_ceil_f64_e32 79 define amdgpu_kernel void @fceil_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) { 80 %y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone 81 store <8 x double> %y, <8 x double> addrspace(1)* %out 82 ret void 83 } 84 85 ; FUNC-LABEL: {{^}}fceil_v16f64: 86 ; CI: v_ceil_f64_e32 87 ; CI: v_ceil_f64_e32 88 ; CI: v_ceil_f64_e32 89 ; CI: v_ceil_f64_e32 90 ; CI: v_ceil_f64_e32 91 ; CI: v_ceil_f64_e32 92 ; CI: v_ceil_f64_e32 93 ; CI: v_ceil_f64_e32 94 ; CI: v_ceil_f64_e32 95 ; CI: v_ceil_f64_e32 96 ; CI: v_ceil_f64_e32 97 ; CI: v_ceil_f64_e32 98 ; CI: v_ceil_f64_e32 99 ; CI: v_ceil_f64_e32 100 ; CI: v_ceil_f64_e32 101 ; CI: v_ceil_f64_e32 102 define amdgpu_kernel void @fceil_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) { 103 %y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone 104 store <16 x double> %y, <16 x double> addrspace(1)* %out 105 ret void 106 } 107
