1 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=CIVI %s 2 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GFX89 -check-prefix=GCN -check-prefix=CIVI %s 3 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX89 -check-prefix=GFX9 -check-prefix=GCN %s 4 5 ; GCN-LABEL: {{^}}fneg_fabs_fadd_f16: 6 ; CI-DAG: v_cvt_f32_f16_e32 7 ; CI-DAG: v_cvt_f32_f16_e64 [[CVT_ABS_X:v[0-9]+]], |s{{[0-9]+}}| 8 ; CI: v_sub_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[CVT_ABS_X]] 9 10 ; GFX89-NOT: _and 11 ; GFX89: v_sub_f16_e64 {{v[0-9]+}}, {{s[0-9]+}}, |{{v[0-9]+}}| 12 define amdgpu_kernel void @fneg_fabs_fadd_f16(half addrspace(1)* %out, half %x, half %y) { 13 %fabs = call half @llvm.fabs.f16(half %x) 14 %fsub = fsub half -0.0, %fabs 15 %fadd = fadd half %y, %fsub 16 store half %fadd, half addrspace(1)* %out, align 2 17 ret void 18 } 19 20 ; GCN-LABEL: {{^}}fneg_fabs_fmul_f16: 21 ; CI-DAG: v_cvt_f32_f16_e32 22 ; CI-DAG: v_cvt_f32_f16_e64 [[CVT_NEG_ABS_X:v[0-9]+]], -|{{s[0-9]+}}| 23 ; CI: v_mul_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, [[CVT_NEG_ABS_X]] 24 ; CI: v_cvt_f16_f32_e32 25 26 ; GFX89-NOT: _and 27 ; GFX89: v_mul_f16_e64 [[MUL:v[0-9]+]], {{s[0-9]+}}, -|{{v[0-9]+}}| 28 ; GFX89-NOT: [[MUL]] 29 ; GFX89: {{flat|global}}_store_short v{{\[[0-9]+:[0-9]+\]}}, [[MUL]] 30 define amdgpu_kernel void @fneg_fabs_fmul_f16(half addrspace(1)* %out, half %x, half %y) { 31 %fabs = call half @llvm.fabs.f16(half %x) 32 %fsub = fsub half -0.0, %fabs 33 %fmul = fmul half %y, %fsub 34 store half %fmul, half addrspace(1)* %out, align 2 35 ret void 36 } 37 38 ; DAGCombiner will transform: 39 ; (fabs (f16 bitcast (i16 a))) => (f16 bitcast (and (i16 a), 0x7FFFFFFF)) 40 ; unless isFabsFree returns true 41 42 ; GCN-LABEL: {{^}}fneg_fabs_free_f16: 43 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000 44 define amdgpu_kernel void @fneg_fabs_free_f16(half addrspace(1)* %out, i16 %in) { 45 %bc = bitcast i16 %in to half 46 %fabs = call half @llvm.fabs.f16(half %bc) 47 %fsub = fsub half -0.0, %fabs 48 store half %fsub, half addrspace(1)* %out 49 ret void 50 } 51 52 ; GCN-LABEL: {{^}}fneg_fabs_f16: 53 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000 54 define amdgpu_kernel void @fneg_fabs_f16(half addrspace(1)* %out, half %in) { 55 %fabs = call half @llvm.fabs.f16(half %in) 56 %fsub = fsub half -0.0, %fabs 57 store half %fsub, half addrspace(1)* %out, align 2 58 ret void 59 } 60 61 ; GCN-LABEL: {{^}}v_fneg_fabs_f16: 62 ; GCN: v_or_b32_e32 v{{[0-9]+}}, 0x8000, v{{[0-9]+}} 63 define amdgpu_kernel void @v_fneg_fabs_f16(half addrspace(1)* %out, half addrspace(1)* %in) { 64 %val = load half, half addrspace(1)* %in, align 2 65 %fabs = call half @llvm.fabs.f16(half %val) 66 %fsub = fsub half -0.0, %fabs 67 store half %fsub, half addrspace(1)* %out, align 2 68 ret void 69 } 70 71 ; GCN-LABEL: {{^}}s_fneg_fabs_v2f16_non_bc_src: 72 ; GFX9-DAG: s_load_dword [[VAL:s[0-9]+]] 73 ; GFX9-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x40003c00 74 ; GFX9: v_pk_add_f16 [[ADD:v[0-9]+]], [[VAL]], [[K]] 75 ; GFX9: v_or_b32_e32 [[RESULT:v[0-9]+]], 0x80008000, [[ADD]] 76 77 ; VI: v_or_b32_e32 v{{[0-9]+}}, 0x80008000, v{{[0-9]+}} 78 define amdgpu_kernel void @s_fneg_fabs_v2f16_non_bc_src(<2 x half> addrspace(1)* %out, <2 x half> %in) { 79 %add = fadd <2 x half> %in, <half 1.0, half 2.0> 80 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %add) 81 %fneg.fabs = fsub <2 x half> <half -0.0, half -0.0>, %fabs 82 store <2 x half> %fneg.fabs, <2 x half> addrspace(1)* %out 83 ret void 84 } 85 86 ; FIXME: single bit op 87 88 ; Combine turns this into integer op when bitcast source (from load) 89 90 ; GCN-LABEL: {{^}}s_fneg_fabs_v2f16_bc_src: 91 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008000 92 define amdgpu_kernel void @s_fneg_fabs_v2f16_bc_src(<2 x half> addrspace(1)* %out, <2 x half> %in) { 93 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in) 94 %fneg.fabs = fsub <2 x half> <half -0.0, half -0.0>, %fabs 95 store <2 x half> %fneg.fabs, <2 x half> addrspace(1)* %out 96 ret void 97 } 98 99 ; GCN-LABEL: {{^}}fneg_fabs_v4f16: 100 ; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0x80008000 101 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[MASK]] 102 ; GCN: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[MASK]] 103 ; GCN: {{flat|global}}_store_dwordx2 104 define amdgpu_kernel void @fneg_fabs_v4f16(<4 x half> addrspace(1)* %out, <4 x half> %in) { 105 %fabs = call <4 x half> @llvm.fabs.v4f16(<4 x half> %in) 106 %fsub = fsub <4 x half> <half -0.0, half -0.0, half -0.0, half -0.0>, %fabs 107 store <4 x half> %fsub, <4 x half> addrspace(1)* %out 108 ret void 109 } 110 111 ; GCN-LABEL: {{^}}fold_user_fneg_fabs_v2f16: 112 ; CI: s_load_dword [[IN:s[0-9]+]] 113 ; CI: s_or_b32 [[FNEG_FABS:s[0-9]+]], [[IN]], 0x80008000 114 ; CI: s_lshr_b32 115 ; CI: v_cvt_f32_f16_e32 v{{[0-9]+}}, s{{[0-9]+}} 116 ; CI: v_cvt_f32_f16_e32 v{{[0-9]+}}, s{{[0-9]+}} 117 ; CI: v_mul_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}} 118 ; CI: v_mul_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}} 119 120 ; VI: v_mul_f16_e64 v{{[0-9]+}}, -|s{{[0-9]+}}|, 4.0 121 ; VI: v_mul_f16_sdwa v{{[0-9]+}}, -|v{{[0-9]+}}|, v{{[0-9]+}} dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD 122 123 ; GFX9: s_and_b32 [[ABS:s[0-9]+]], s{{[0-9]+}}, 0x7fff7fff 124 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, [[ABS]], 4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] 125 define amdgpu_kernel void @fold_user_fneg_fabs_v2f16(<2 x half> addrspace(1)* %out, <2 x half> %in) #0 { 126 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in) 127 %fneg.fabs = fsub <2 x half> <half -0.0, half -0.0>, %fabs 128 %mul = fmul <2 x half> %fneg.fabs, <half 4.0, half 4.0> 129 store <2 x half> %mul, <2 x half> addrspace(1)* %out 130 ret void 131 } 132 133 ; GCN-LABEL: {{^}}s_fneg_multi_use_fabs_v2f16: 134 ; GFX9: s_and_b32 [[ABS:s[0-9]+]], s{{[0-9]+}}, 0x7fff7fff 135 ; GFX9: v_mov_b32_e32 [[V_ABS:v[0-9]+]], [[ABS]] 136 ; GFX9: s_xor_b32 [[NEG:s[0-9]+]], [[ABS]], 0x80008000 137 ; GFX9-DAG: v_mov_b32_e32 [[V_NEG:v[0-9]+]], [[NEG]] 138 ; GFX9-DAG: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[V_ABS]] 139 ; GFX9: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[V_NEG]] 140 define amdgpu_kernel void @s_fneg_multi_use_fabs_v2f16(<2 x half> addrspace(1)* %out0, <2 x half> addrspace(1)* %out1, <2 x half> %in) { 141 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in) 142 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %fabs 143 store <2 x half> %fabs, <2 x half> addrspace(1)* %out0 144 store <2 x half> %fneg, <2 x half> addrspace(1)* %out1 145 ret void 146 } 147 148 ; GCN-LABEL: {{^}}s_fneg_multi_use_fabs_foldable_neg_v2f16: 149 ; GFX9: s_and_b32 [[ABS:s[0-9]+]], s{{[0-9]+}}, 0x7fff7fff 150 ; GFX9: v_pk_mul_f16 v{{[0-9]+}}, [[ABS]], 4.0 op_sel_hi:[1,0] neg_lo:[1,0] neg_hi:[1,0] 151 define amdgpu_kernel void @s_fneg_multi_use_fabs_foldable_neg_v2f16(<2 x half> addrspace(1)* %out0, <2 x half> addrspace(1)* %out1, <2 x half> %in) { 152 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in) 153 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %fabs 154 %mul = fmul <2 x half> %fneg, <half 4.0, half 4.0> 155 store <2 x half> %fabs, <2 x half> addrspace(1)* %out0 156 store <2 x half> %mul, <2 x half> addrspace(1)* %out1 157 ret void 158 } 159 160 declare half @llvm.fabs.f16(half) #1 161 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #1 162 declare <4 x half> @llvm.fabs.v4f16(<4 x half>) #1 163 164 attributes #0 = { nounwind } 165 attributes #1 = { nounwind readnone } 166
