1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s 3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s 4 5 ; FUNC-LABEL: {{^}}s_fneg_f32: 6 ; R600: -PV 7 8 ; GCN: v_xor_b32 9 define amdgpu_kernel void @s_fneg_f32(float addrspace(1)* %out, float %in) { 10 %fneg = fsub float -0.000000e+00, %in 11 store float %fneg, float addrspace(1)* %out 12 ret void 13 } 14 15 ; FUNC-LABEL: {{^}}s_fneg_v2f32: 16 ; R600: -PV 17 ; R600: -PV 18 19 ; GCN: v_xor_b32 20 ; GCN: v_xor_b32 21 define amdgpu_kernel void @s_fneg_v2f32(<2 x float> addrspace(1)* nocapture %out, <2 x float> %in) { 22 %fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in 23 store <2 x float> %fneg, <2 x float> addrspace(1)* %out 24 ret void 25 } 26 27 ; FUNC-LABEL: {{^}}s_fneg_v4f32: 28 ; R600: -PV 29 ; R600: -T 30 ; R600: -PV 31 ; R600: -PV 32 33 ; GCN: v_xor_b32 34 ; GCN: v_xor_b32 35 ; GCN: v_xor_b32 36 ; GCN: v_xor_b32 37 define amdgpu_kernel void @s_fneg_v4f32(<4 x float> addrspace(1)* nocapture %out, <4 x float> %in) { 38 %fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %in 39 store <4 x float> %fneg, <4 x float> addrspace(1)* %out 40 ret void 41 } 42 43 ; DAGCombiner will transform: 44 ; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000)) 45 ; unless the target returns true for isNegFree() 46 47 ; FUNC-LABEL: {{^}}fsub0_f32: 48 49 ; GCN: v_sub_f32_e64 v{{[0-9]}}, 0, s{{[0-9]+$}} 50 51 ; R600-NOT: XOR 52 ; R600: -KC0[2].Z 53 define amdgpu_kernel void @fsub0_f32(float addrspace(1)* %out, i32 %in) { 54 %bc = bitcast i32 %in to float 55 %fsub = fsub float 0.0, %bc 56 store float %fsub, float addrspace(1)* %out 57 ret void 58 } 59 ; FUNC-LABEL: {{^}}fneg_free_f32: 60 ; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb 61 ; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c 62 63 ; GCN: v_bfrev_b32_e32 [[SIGNBIT:v[0-9]+]], 1{{$}} 64 ; GCN: v_xor_b32_e32 [[RES:v[0-9]+]], [[NEG_VALUE]], [[SIGNBIT]] 65 ; GCN: buffer_store_dword [[RES]] 66 67 ; R600-NOT: XOR 68 ; R600: -PV.W 69 define amdgpu_kernel void @fneg_free_f32(float addrspace(1)* %out, i32 %in) { 70 %bc = bitcast i32 %in to float 71 %fsub = fsub float -0.0, %bc 72 store float %fsub, float addrspace(1)* %out 73 ret void 74 } 75 76 ; FUNC-LABEL: {{^}}fneg_fold_f32: 77 ; SI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb 78 ; VI: s_load_dword [[NEG_VALUE:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c 79 ; GCN-NOT: xor 80 ; GCN: v_mul_f32_e64 v{{[0-9]+}}, -[[NEG_VALUE]], [[NEG_VALUE]] 81 define amdgpu_kernel void @fneg_fold_f32(float addrspace(1)* %out, float %in) { 82 %fsub = fsub float -0.0, %in 83 %fmul = fmul float %fsub, %in 84 store float %fmul, float addrspace(1)* %out 85 ret void 86 } 87 88 ; Make sure we turn some integer operations back into fabs 89 ; FUNC-LABEL: {{^}}bitpreserve_fneg_f32: 90 ; GCN: v_mul_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -4.0 91 define amdgpu_kernel void @bitpreserve_fneg_f32(float addrspace(1)* %out, float %in) { 92 %in.bc = bitcast float %in to i32 93 %int.abs = xor i32 %in.bc, 2147483648 94 %bc = bitcast i32 %int.abs to float 95 %fadd = fmul float %bc, 4.0 96 store float %fadd, float addrspace(1)* %out 97 ret void 98 } 99
