1 # RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s 2 # RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s 3 4 # GCN-LABEL: name: hazard_implicit_def 5 # GCN: bb.0.entry: 6 # GCN: $m0 = S_MOV_B32 7 # GFX9: S_NOP 0 8 # VI-NOT: S_NOP_0 9 # GCN: V_INTERP_P1_F32 10 11 --- 12 name: hazard_implicit_def 13 alignment: 0 14 exposesReturnsTwice: false 15 legalized: false 16 regBankSelected: false 17 selected: false 18 tracksRegLiveness: true 19 registers: 20 liveins: 21 - { reg: '$sgpr7', virtual-reg: '' } 22 - { reg: '$vgpr4', virtual-reg: '' } 23 body: | 24 bb.0.entry: 25 liveins: $sgpr7, $vgpr4 26 27 $m0 = S_MOV_B32 killed $sgpr7 28 $vgpr5 = IMPLICIT_DEF 29 $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $m0, implicit $exec 30 SI_RETURN_TO_EPILOG killed $vgpr5, killed $vgpr0 31 32 ... 33 34 # GCN-LABEL: name: hazard_inlineasm 35 # GCN: bb.0.entry: 36 # GCN: $m0 = S_MOV_B32 37 # GFX9: S_NOP 0 38 # VI-NOT: S_NOP_0 39 # GCN: V_INTERP_P1_F32 40 --- 41 name: hazard_inlineasm 42 alignment: 0 43 exposesReturnsTwice: false 44 legalized: false 45 regBankSelected: false 46 selected: false 47 tracksRegLiveness: true 48 registers: 49 liveins: 50 - { reg: '$sgpr7', virtual-reg: '' } 51 - { reg: '$vgpr4', virtual-reg: '' } 52 body: | 53 bb.0.entry: 54 liveins: $sgpr7, $vgpr4 55 56 $m0 = S_MOV_B32 killed $sgpr7 57 INLINEASM &"; no-op", 1, 327690, def $vgpr5 58 $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $m0, implicit $exec 59 SI_RETURN_TO_EPILOG killed $vgpr5, killed $vgpr0 60 ... 61
