1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s 2 3 ; Check that invariant compare is hoisted out of the loop. 4 ; At the same time condition shall not be serialized into a VGPR and deserialized later 5 ; using another v_cmp + v_cndmask, but used directly in s_and_saveexec_b64. 6 7 ; CHECK: v_cmp_{{..}}_u32_e{{32|64}} [[COND:s\[[0-9]+:[0-9]+\]|vcc]] 8 ; CHECK: BB0_1: 9 ; CHECK-NOT: v_cmp 10 ; CHECK_NOT: v_cndmask 11 ; CHECK: s_and_saveexec_b64 s[{{[[0-9]+:[0-9]+}}], [[COND]] 12 ; CHECK: BB0_2: 13 14 define amdgpu_kernel void @hoist_cond(float addrspace(1)* nocapture %arg, float addrspace(1)* noalias nocapture readonly %arg1, i32 %arg3, i32 %arg4) { 15 bb: 16 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 17 %tmp5 = icmp ult i32 %tmp, %arg3 18 br label %bb1 19 20 bb1: ; preds = %bb3, %bb 21 %tmp7 = phi i32 [ %arg4, %bb ], [ %tmp16, %bb3 ] 22 %tmp8 = phi float [ 0.000000e+00, %bb ], [ %tmp15, %bb3 ] 23 br i1 %tmp5, label %bb2, label %bb3 24 25 bb2: ; preds = %bb1 26 %tmp10 = zext i32 %tmp7 to i64 27 %tmp11 = getelementptr inbounds float, float addrspace(1)* %arg1, i64 %tmp10 28 %tmp12 = load float, float addrspace(1)* %tmp11, align 4 29 br label %bb3 30 31 bb3: ; preds = %bb2, %bb1 32 %tmp14 = phi float [ %tmp12, %bb2 ], [ 0.000000e+00, %bb1 ] 33 %tmp15 = fadd float %tmp8, %tmp14 34 %tmp16 = add i32 %tmp7, -1 35 %tmp17 = icmp eq i32 %tmp16, 0 36 br i1 %tmp17, label %bb4, label %bb1 37 38 bb4: ; preds = %bb3 39 store float %tmp15, float addrspace(1)* %arg, align 4 40 ret void 41 } 42 43 ; Function Attrs: nounwind readnone 44 declare i32 @llvm.amdgcn.workitem.id.x() #0 45 46 attributes #0 = { nounwind readnone } 47
