1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s 3 4 ; SI-LABEL: {{^}}i1_copy_from_loop: 5 ; 6 ; Cannot use an SGPR mask to copy %cc out of the loop, since the mask would 7 ; only contain the lanes that were active during the last loop iteration. 8 ; 9 ; SI: ; %for.body 10 ; SI: v_cmp_gt_u32_e64 [[SREG:s\[[0-9]+:[0-9]+\]]], 4, 11 ; SI: v_cndmask_b32_e64 [[VREG:v[0-9]+]], 0, -1, [[SREG]] 12 ; SI-NEXT: s_cbranch_vccnz [[ENDIF:BB[0-9_]+]] 13 ; SI: [[ENDIF]]: 14 ; SI-NOT: [[VREG]] 15 ; SI: ; %for.end 16 ; SI: v_cmp_ne_u32_e32 vcc, 0, [[VREG]] 17 define amdgpu_ps void @i1_copy_from_loop(<4 x i32> inreg %rsrc, i32 %tid) { 18 entry: 19 br label %for.body 20 21 for.body: 22 %i = phi i32 [0, %entry], [%i.inc, %end.loop] 23 %cc = icmp ult i32 %i, 4 24 br i1 %cc, label %mid.loop, label %for.end 25 26 mid.loop: 27 %v = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %tid, i32 %i, i1 false, i1 false) 28 %cc2 = fcmp oge float %v, 0.0 29 br i1 %cc2, label %end.loop, label %for.end 30 31 end.loop: 32 %i.inc = add i32 %i, 1 33 br label %for.body 34 35 for.end: 36 br i1 %cc, label %if, label %end 37 38 if: 39 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float undef, float undef, float undef, float undef, i1 true, i1 true) 40 br label %end 41 42 end: 43 ret void 44 } 45 46 declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0 47 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1 48 49 attributes #0 = { nounwind readonly } 50 attributes #1 = { nounwind inaccessiblememonly } 51
